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Cadence Design Systems Inc (CDNS) provides critical electronic design automation (EDA) software and semiconductor intellectual property solutions powering modern chip development. This news hub offers investors and industry professionals centralized access to official announcements and market-relevant updates.
Track earnings reports, product launches, and strategic partnerships shaping the EDA landscape. Our curated collection ensures timely access to developments impacting semiconductor design innovation across automotive, AI hardware, and IoT sectors.
Discover how Cadence's tools in digital verification, custom IP blocks, and system-level integration address evolving industry challenges. Bookmark this page for streamlined monitoring of operational milestones and technology advancements directly from the source.
Cadence is collaborating with NVIDIA to accelerate the sustainability of AI factories (data centers) using digital twins. By integrating NVIDIA Omniverse technologies into Cadence's Reality Digital Twin Platform, they aim to improve data center efficiency and utilization by up to 40%, reducing AI's energy footprint.
The partnership focuses on developing digital twin models for NVIDIA's A100 and H100 GPUs, and GB200 systems, using OpenUSD for standardization. This approach enables precise simulations of performance, resource utilization, and thermal dynamics in data center environments.
The initiative aims to enhance the design, deployment, and operation of AI factories, promoting sustainable computing practices through smart resource management and improved regulatory compliance. By leveraging digital twins, stakeholders can optimize operations, reduce environmental impact, and drive innovation in the data center industry.
Cadence Design Systems (Nasdaq: CDNS) has launched Fem.AI, an initiative aimed at promoting gender equity in the AI workforce. The Cadence Giving Foundation has pledged $20 million over the next decade to support this cause through philanthropic and product donations. The initiative addresses three key challenges for women in AI: completing higher education, accessing first jobs, and retaining STEM careers.
Cadence's research shows that only 20% of computer science graduates are female, women hold just over 20% of AI roles in US tech companies, and over 56% of women in tech are likely to leave the industry before mid-career. To tackle these issues, Cadence has partnered with various nonprofits and will host the inaugural Fem.AI Summit on October 1 in Menlo Park, bringing together leaders from business, academia, media, and social impact sectors to promote cross-sector collaboration.
Cadence Design Systems explores how data centers can leverage digital twin technology to address the challenges posed by AI's increasing energy demands while transitioning to renewable energy solutions. The article highlights that:
1. AI queries consume significantly more energy than standard searches.
2. European data center demand is outpacing supply.
3. Digital twins offer benefits such as energy efficiency testing, enhanced resource allocation, and data-driven decision-making.
4. This technology can help data centers optimize operations, improve sustainability metrics, and comply with regulations.
The article concludes that by adopting digital twin technology, data centers can better manage energy demands, integrate renewable solutions, and lead the charge towards a greener future in the face of AI growth and sustainability pressures.
Cadence Design Systems emphasizes the importance of allyship in the workplace, citing a report that shows 92% of individuals find allies invaluable in their careers. The company's culture promotes diversity, inclusion, and meaningful connections through various initiatives. An employee shares their personal journey of allyship, highlighting how it has shaped their life and professional experiences. The narrative underscores how embracing diverse perspectives and forging relationships can ignite allyship, leading to a more inclusive work environment. Cadence encourages employees to engage in allyship, viewing it as essential for innovation and collective success.
Cadence Design Systems (CDNS) reported strong Q2 2024 financial results, with revenue of $1.061 billion, up from $977 million in Q2 2023. The company's GAAP operating margin was 28%, while non-GAAP operating margin was 40%. GAAP diluted EPS reached $0.84, and non-GAAP diluted EPS was $1.28. Cadence's quarter-end backlog stood at $6.0 billion, with current remaining performance obligations of $3.1 billion.
The company updated its 2024 revenue outlook to 13% year-over-year growth, expecting revenue between $4.60 billion and $4.66 billion. Cadence's Cadence.AI portfolio and next-generation Z3/X3 hardware systems showed strong momentum, with robust demand from AI, hyperscale, and automotive customers. The company also completed the BETA CAE acquisition, expanding its multiphysics platform offerings.
Cadence Design Systems celebrated Pride Month with global events highlighting their commitment to diversity, equity, and inclusion (DEI). Key activities included:
Flag raising ceremonies worldwide, displaying the Pride Progress Flag at various office sites.
An enlightening conversation with Megan Smith, former US Chief Technology Officer, who discussed technology, diversity, and social change.
The second annual Cadence Pridefest at headquarters, featuring LGBTQ+-owned businesses and community organizations.
These events aimed to foster inclusivity, support the LGBTQ+ community, and reinforce Cadence's dedication to creating a diverse and equitable workplace in the tech industry.
Cadence Design Systems (Nasdaq: CDNS) will host a webcast for their second quarter 2024 financial results on July 22, 2024. The webcast, featuring CEO Dr. Anirudh Devgan and CFO John Wall, will commence at 2:00 p.m. Pacific Time. The event will be archived and accessible online from 5:00 p.m. PT on July 22 until 5:00 p.m. PT on September 13, 2024, at cadence.com/cadence/investor_relations.
Cadence Design Systems has expanded its system IP portfolio with the Cadence Janus Network-on-Chip (NoC). This addition aims to address the increased complexity and data delivery challenges within and between silicon components in larger SoCs and disaggregated multi-chip systems. The Janus NoC enhances power, performance, and area (PPA) targets, reducing latency and freeing engineering resources for SoC differentiation. Leveraging Cadence's Tensilica RTL tools, the NoC allows for extensive simulation and emulation, aiding in architectural exploration and mitigating routing congestion and timing issues. The Janus NoC will be available in July 2024.
Cadence Design Systems has announced significant achievements in its partnership with Intel Foundry. The collaboration includes advancements in 3D-IC enablement, EDA flows, and IP development for Intel's 18A process nodes.
Key milestones include the availability of a complete EMIB 2.5D advanced packaging flow, enhancements to digital and custom/analog flows, and a comprehensive IP portfolio and PDKs across multiple nodes. Cadence’s AI-driven flows for Intel 18A technology enable efficient design and rapid time-to-market for complex AI-enabling semiconductors. The collaboration leverages Intel’s EMIB technology and advanced silicon capabilities to meet performance, power, and area (PPA) goals.
Cadence’s solutions include the Integrity 3D-IC Platform, Allegro X APD, Sigrity, Clarity 3D Solver, Pegasus Verification System, Virtuoso Studio, Cerebrus Intelligent Chip Explorer, Genus Synthesis Solution, Innovus Implementation System, Quantus Extraction Solution, Tempus Timing Solution, Voltus IC Power Integrity Solution, and Liberate Characterization. The partnership aims to deliver next-generation system innovations and support the development of high-performance computing and AI/ML applications.
Cadence Design Systems announced a collaboration with Samsung Foundry to advance AI and 3D-IC semiconductor design. This partnership focuses on optimizing Cadence.AI digital and analog tools for Samsung's advanced node SF2 GAA. The collaboration aims to minimize leakage power, enhance design flows, and accelerate time to market.
Key achievements include a 10% reduction in leakage power, certification of the Cadence backside implementation flow for SF2, and the success of a test chip using these technologies. Cadence’s 3D-IC technology now supports all of Samsung’s multi-die integration offerings, with innovations in thermal warpage analysis and system-level LVS.
Additionally, Cadence’s Virtuoso Studio and mmWave RFIC design flow have improved analog circuit process migration and the tapeout process for RF designs. Their Pegasus Verification System is now certified for Samsung’s 4nm and 3nm processes, enhancing signoff accuracy and runtime. Cadence’s IP portfolio supports next-gen AI designs, with advanced memory IP for GDDR7. This collaboration underscores a mutual commitment to delivering competitive, next-gen semiconductor solutions.
