Cadence and Rapidus Collaborate on Leading-Edge 2nm Semiconductor Solutions for AI and HPC Applications

Rhea-AI Summary

Cadence Design Systems (CDNS) announced a collaboration with Rapidus to develop co-optimized AI-driven reference design flows and IP portfolio supporting Rapidus' 2nm gate-all-around (GAA) process with backside power delivery network (BSPDN) technology. The partnership aims to address increasing design challenges in the semiconductor industry, focusing on power, performance, and area requirements.

The collaboration includes numerous Cadence solutions, such as Cerebrus Intelligent Chip Explorer, JedAI Solution, and various other digital and analog/mixed signal tools. Customers will have access to Cadence's interface and memory IP components, including HBM4, 224G SerDes, and PCIe 7.0.

Positive

• Strategic collaboration for advanced 2nm semiconductor technology development
• Access to broad portfolio of interface and memory IP components
• Implementation of AI-driven reference design flows

Negative

• None.

Insights

Tech Expert

This strategic collaboration represents a significant technological advancement in semiconductor manufacturing. The 2nm GAA process with BSPDN technology marks a important evolution in chip design, particularly vital for AI and HPC applications. The combination of Rapidus' advanced manufacturing capabilities with Cadence's comprehensive AI-driven design tools and IP portfolio addresses the growing demand for more efficient, powerful computing solutions. The integration of HBM4, 224G SerDes and PCIe 7.0 IP components indicates a focus on high-performance computing applications. The backside power delivery network technology is particularly noteworthy as it enables better power distribution and thermal management, critical factors in advanced chip design.

Market Research Analyst

This partnership strengthens Cadence's position in the high-end semiconductor design market, particularly in the lucrative AI and HPC segments. The collaboration with Rapidus, a key player in Japan's semiconductor industry, opens up strategic opportunities in the Asian market. The timing is optimal given the global push for advanced semiconductor manufacturing capabilities and the increasing demand for AI-specific chips. The comprehensive suite of Cadence tools being deployed, including Cerebrus and JedAI solutions, demonstrates the company's strong competitive position in AI-driven chip design tools. This positions Cadence well to capture value from the growing trend toward more sophisticated chip designs.

Collaboration spans interface and memory IP utilizing 2nm gate-all-around BSPDN technology and AI-driven reference flows to facilitate the development of advanced, energy-efficient chips

SAN JOSE, Calif.--(BUSINESS WIRE)-- Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced it is collaborating with Rapidus Corporation to provide co-optimized AI-driven reference design flows and a broad IP portfolio to support the Rapidus 2nm gate-all-around (GAA) process and leverage the design and manufacturing benefits from Rapidus’ backside power delivery network (BSPDN) technology. As the semiconductor industry struggles to keep up with significantly increasing design challenges driven by the need for more computation, GAA and BSPDN manufacturing technologies are becoming vital to meet increasingly stringent power, performance and area requirements.

The AI-driven digital and analog/mixed signal reference design flows encompass numerous solutions from Cadence, including Cadence^® Cerebrus^™ Intelligent Chip Explorer, Cadence JedAI Solution, Genus^™ Synthesis Solution, Conformal^®, Joules^™ RTL Power Solution, Innovus^™ Implementation System, Tempus^™ Timing Signoff Solution, Quantus^™ Extraction Solution, Voltus IC Power Integrity Solution^™, Virtuoso^® Studio, Spectre^® X Simulator, Voltus^™-XFi Custom Power Integrity Solution, and Pegasus^™ Verification System. Customers will be able to use a broad portfolio of Cadence interface and memory IP components, including HBM4, 224G SerDes, and PCI Express^® (PCIe^®) 7.0.

“Our collaboration with Cadence on 2nm BSPDN technology puts us at the industry’s forefront, marking a major leap in semiconductor innovation for performance and efficiency. By combining our expertise, we’re excited to set new technology standards and create transformative solutions for our mutual customers and the industry,” said Dr. Atsuyoshi Koike, CEO of Rapidus.

“Our broad collaboration with Rapidus for 2nm GAA BSPDN technology leverages Cadence’s AI-driven solutions to solve real-world problems and meet customer needs,” said Dr. Anirudh Devgan, president and CEO at Cadence. “By bringing together Cadence’s advanced interface and memory IP technology, reference flows and Rapidus’ process technology, we're empowering the buildout of the AI infrastructure of tomorrow.”

About Cadence

Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware, and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare. For 10 years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.

© 2024 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. PCI Express and PCIe are registered trademarks of PCI-SIG. All other trademarks are the property of their respective owners.

Category: Featured

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Source: Cadence Design Systems, Inc.

FAQ

What is the purpose of Cadence (CDNS) and Rapidus' collaboration on 2nm semiconductor technology?

The collaboration aims to provide co-optimized AI-driven reference design flows and IP portfolio support for Rapidus' 2nm GAA process with BSPDN technology, addressing increasing design challenges in power, performance, and area requirements.

What key technologies will be available through the CDNS and Rapidus partnership?

The partnership will provide access to Cadence's interface and memory IP components, including HBM4, 224G SerDes, and PCIe 7.0, along with AI-driven digital and analog/mixed signal reference design flows.

How does the CDNS-Rapidus 2nm collaboration benefit semiconductor design?

The collaboration leverages AI-driven solutions and BSPDN technology to solve real-world problems, improve efficiency, and meet increasingly stringent power, performance, and area requirements in semiconductor design.

What Cadence (CDNS) solutions are included in the 2nm semiconductor collaboration?

The collaboration includes Cerebrus Intelligent Chip Explorer, JedAI Solution, Genus Synthesis Solution, Conformal, and various other digital and analog/mixed signal tools from Cadence.