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Synopsys Advances Power and Performance for AI and Multi-Die Designs on Latest Samsung Foundry Processes at SAFE Forum 2026

Rhea-AI Impact
(Moderate)
Rhea-AI Sentiment
(Positive)
Tags
AI

Synopsys (Nasdaq: SNPS) announced expanded collaboration with Samsung Foundry at SAFE Forum 2026, introducing production‑ready, AI‑powered digital and analog flows for second- and third‑generation 2nm processes and certified interface IP.

Key updates include up to 20% test efficiency gains, signoff frequency improvement of up to 2.7%, new 3DIC multiphysics signoff, and broader IP support for advanced and automotive nodes.

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AI-generated analysis. Not financial advice.

Positive

  • Production‑ready AI‑powered digital and analog flows for third‑generation 2nm processes
  • Frequency improvement up to 2.7% at signoff with PrimeShield multiphysics analysis
  • Test patterns and cycles reduced up to 20% using TestMAX with AI ATPG
  • Certified 3DIC multiphysics signoff on Hybrid Copper Bonding 3D test chip
  • Expanded interface and foundation IP portfolio across 14nm to second‑generation 2nm nodes
  • Automotive‑grade IP support at 5nm and 2nm class Samsung processes

Negative

  • None.

News Market Reaction – SNPS

-8.61% 2.2x vol
95 alerts
-8.61% News Effect
-6.3% Trough in 5 hr 42 min
-$9.09B Valuation Impact
$96.48B Market Cap
2.2x Rel. Volume

On the day this news was published, SNPS declined 8.61%, reflecting a notable negative market reaction. Argus tracked a trough of -6.3% from its starting point during tracking. Our momentum scanner triggered 95 alerts that day, indicating high trading interest and price volatility. This price movement removed approximately $9.09B from the company's valuation, bringing the market cap to $96.48B at that time. Trading volume was elevated at 2.2x the daily average, suggesting increased selling activity.

Data tracked by StockTitan Argus on the day of publication.

Key Figures

Test efficiency gain: up to 20% Frequency improvement: up to 2.7% Leakage change: 5% leakage current degradation +2 more
5 metrics
Test efficiency gain up to 20% Customers’ test efficiency improvement using AI-powered, silicon-based test capabilities
Frequency improvement up to 2.7% PrimeShield Process Sensitivity Analysis and PVT Explorer during signoff
Leakage change 5% leakage current degradation Tradeoff associated with frequency improvement in 2nm-class signoff optimization
Test reduction up to 20% Reduction in test patterns and test cycles with TestMAX TSO.ai on Samsung nodes
Process nodes 14nm, 8nm, 5nm, 4nm, 2nm Range of Samsung Foundry processes supported by Synopsys IP portfolio

Market Reality Check

Price: $475.62 Vol: Volume 2.36M is 49% above...
normal vol
$475.62 Last Close
Volume Volume 2.36M is 49% above 20-day average 1.58M, indicating elevated trading interest pre-news. normal
Technical Price $525.92 is trading about 12% above 200-day MA $470.46, reflecting a longer-term uptrend.

Peers on Argus

SNPS is down 1.62% while momentum peers like NET, IOT, and MDB show gains of abo...
3 Up

SNPS is down 1.62% while momentum peers like NET, IOT, and MDB show gains of about 7.8–10.7%, indicating today’s weakness is stock-specific rather than a sector-wide AI/software move.

Previous AI Reports

5 past events · Latest: Mar 11 (Positive)
Same Type Pattern 5 events
Date Event Sentiment Move Catalyst
Mar 11 AI product launch Positive +0.1% Launch of Ansys 2026 R1 with expanded AI-driven simulation and workflows.
Mar 11 AI verification update Positive +0.1% Software-defined hardware-assisted verification with up to 2x performance and capacity.
Mar 10 AI platform launch Positive -1.1% Launch of Electronics Digital Twin Platform for physical AI system development.
Jan 06 AI automotive showcase Positive +3.0% Showcase of AI-driven automotive engineering with large testing cost reductions.
Oct 28 AI GPU acceleration Positive -1.8% Highlighting agentic AI and GPU-accelerated engineering at NVIDIA GTC.
Pattern Detected

AI-related launches often trigger modest moves for SNPS, with a mix of small gains and occasional declines around such announcements.

Recent Company History

Over recent months, Synopsys has repeatedly highlighted AI-powered platforms and workflows, from the Electronics Digital Twin Platform on Mar 10, 2026 to multiple AI-focused launches on Mar 11, 2026 and AI engineering showcases at CES 2026. Market reactions to these AI announcements have generally been modest, with single-day moves clustered around small gains or losses. Today’s Samsung Foundry collaboration extends this AI and advanced-node narrative, reinforcing Synopsys’ positioning across design, verification, and digital twin use cases.

Historical Comparison

+0.0% avg move · Over the last five AI-tagged announcements, SNPS saw an average 0.04% one-day move, suggesting histo...
AI
+0.0%
Average Historical Move AI

Over the last five AI-tagged announcements, SNPS saw an average 0.04% one-day move, suggesting historically muted price reactions to AI-focused product and platform news.

AI news shows a steady expansion from simulation and digital twin platforms into broader hardware-assisted verification and automotive engineering, indicating a consistent push to embed AI across Synopsys’ toolchain.

Market Pulse Summary

The stock moved -8.6% in the session following this news. A negative reaction despite AI-focused col...
Analysis

The stock moved -8.6% in the session following this news. A negative reaction despite AI-focused collaboration news fits prior instances where upbeat AI announcements coincided with flat or weaker trading, given an average move near 0.04%. In this context, broader concerns from recent filings about GAAP profitability, restructuring, and integration of large acquisitions could have overshadowed product news. Historically mixed responses to AI updates suggest that execution and financial quality remained key focus areas.

Key Terms

design technology co-optimization, electromigration, ir drop, automatic test pattern generation, +4 more
8 terms
design technology co-optimization technical
"Unique Design Technology Co-Optimization (DTCO) initiatives for synthesis and layout..."
Design technology co-optimization is the process of jointly adjusting a product’s design (how a chip is laid out) and the manufacturing steps (how the chip is made) so both work together for the best results. For investors it matters because tighter coordination can reduce production costs, improve performance and yields, and speed time-to-market—like tailoring a suit while choosing the fabric so it fits perfectly and wastes less material.
electromigration technical
"Synopsys Totem-SC is a newly certified electromigration (EM) and IR drop analysis solution..."
Electromigration is the gradual movement of metal atoms inside tiny electrical wires and connections when high-density current flows through them, eventually creating thin spots, voids or short circuits. For investors, it matters because it can reduce the lifespan and reliability of electronic products, raise manufacturing defects and warranty costs, and drive companies to invest in different chip designs, materials or testing processes that affect production costs and competitiveness.
ir drop technical
"Synopsys Totem-SC is a newly certified electromigration (EM) and IR drop analysis solution..."
An IR drop is the loss of electrical voltage that happens when current flows through resistance in a circuit, described by Ohm’s law as current times resistance. For investors, it matters because excessive IR drop in power delivery systems, chips or batteries can reduce device performance, cause overheating, shorten lifespan, and force costly redesigns or recalls — similar to how a narrow pipe reduces water pressure at the tap.
automatic test pattern generation technical
"Synopsys TestMAX with AI-assisted automatic test pattern generation (ATPG) technologies..."
Automatic test pattern generation is software that creates sequences of signals used to probe electronic chips or systems for manufacturing defects and design faults. For investors, it matters because stronger, faster test pattern generation helps catch problems earlier, reducing wasted units and recalls, lowering production costs and shortening time-to-market—like a quality checklist that finds mistakes before a product ships.
3dic technical
"Synopsys 3DIC Compiler, a unified exploration-to-signoff platform being validated..."
3DIC (three-dimensional integrated circuit) is a semiconductor design that stacks multiple chips or layers of circuitry vertically and connects them so they act as a single, compact device. Think of it like stacking floors in a building instead of spreading rooms across a wide plot: it packs more functionality into a smaller space while improving speed and energy efficiency. Investors watch 3DIC adoption because it can lower manufacturing costs per function, enable faster or more power-efficient products, and create competitive advantages for makers of chips and devices, affecting revenue, margins, and market position.
hybrid copper bonding technical
"3DIC Solution with Hybrid Copper Bonding Technology: Synopsys and Samsung Foundry..."
Hybrid copper bonding is an advanced chip-joining technique that physically and electrically links two semiconductor layers using tiny copper contacts alongside surrounding insulating material, creating both direct metal connections and close-surface bonds in one step. For investors it matters because this method can greatly increase speed, reduce power use and shrink package size—like replacing tangled cords between devices with a neat, high-speed connector—affecting product performance, manufacturing cost, and supply-chain competitiveness.
ucie technical
"interface IP—including UCIe, PCIe 7.0, 112G/224G, MIPI, LPDDR6, DDR5 MRDIMM Gen2..."
UCIe (Universal Chiplet Interconnect Express) is an industry standard for connecting small processor or memory building blocks, called chiplets, inside a single package so they work together like parts of a single chip. For investors, it matters because it can lower manufacturing costs, speed product development, and enable more flexible, high-performance semiconductors—similar to using interchangeable Lego pieces instead of carving one large block—potentially affecting makers’ competitiveness and profit margins.
pcie 7.0 technical
"interface IP—including UCIe, PCIe 7.0, 112G/224G, MIPI, LPDDR6, DDR5 MRDIMM Gen2..."
PCIe 7.0 is the latest generation of the PCI Express standard, the high-speed electrical interface that lets core computer parts—processors, graphics cards, storage drives and network cards—move large amounts of data between each other. It matters to investors because each new PCIe version enables faster, more efficient servers and devices, spurs demand for upgraded chips and hardware, and can influence sales cycles, margins and competitive positions in semiconductors and data-center equipment; think of it as widening a digital highway to allow much higher traffic flow.

AI-generated analysis. Not financial advice.

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Highlights:

  • New production-ready, AI-powered digital and analog flows are available for second-and third-generation 2nm processes accompanied by an expanded portfolio of certified interface IP, including for Samsung Foundry's automotive nodes.
  • Unique Design Technology Co-Optimization (DTCO) initiatives for synthesis and layout, as well as signoff, are delivering meaningful power, performance, and area (PPA) enhancements.
  • Customers are observing significant test efficiency improvements of up to 20% by leveraging AI-powered, silicon-based design and manufacturing test capabilities validated and deployed in collaboration with Samsung Foundry.

SUNNYVALE, Calif., May 28, 2026 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today announced at Samsung Advanced Foundry Ecosystem (SAFE) Forum 2026 its latest collaborations with Samsung Foundry on advanced nodes, including an expanded portfolio of production‑ready, AI-powered EDA tools, certified interface IP, and silicon-based test capabilities, enabling customers to bring differentiated AI and multi-die designs to market faster and with measurably improved quality.

During his keynote at the event, Synopsys President and CEO Sassine Ghazi underscored the companies' long-standing collaboration to address compounding semiconductor engineering complexity, intense pressure for faster development cycles, and increasing costs. Ghazi emphasized that overcoming these challenges requires a fundamentally new approach where AI driven automation and multiphysics intelligence are fused across the entire design and manufacturing flow. Pointing to initiatives leveraging Synopsys AI-powered solutions and deep design and technology co optimization (DTCO), Ghazi said customers are bringing advanced silicon to market faster, while achieving meaningful gains in PPA and test efficiency, on Samsung Foundry's latest process nodes. 

"Close alignment across design, test, and manufacturing are critical to the success of AI and multi-die designs on advanced nodes," said Hyung‑Ock Kim, vice president and head of the Foundry Design Technology Team at Samsung Electronics. "Our continued close collaboration with Synopsys delivers silicon-based, customer-validated solutions that help our customers reduce design integration risk, improve silicon predictability, and move confidently from design to production for their most innovative solutions."

"As designs become more heterogeneous, customers need production‑ready, silicon-proven solutions that address complexity and minimize risk from silicon to systems," said Ravi Subramanian, Chief Product Management Officer at Synopsys. "Our work with Samsung Foundry translates years of DTCO and silicon learning into enablement that helps our customers get their advanced designs to market quickly and with confidence."

The latest Synopsys and Samsung Foundry collaborations include:

  • New Synopsys Production-Ready Flows and Improved PPA on third-generation 2nm class process: Synopsys AI-powered digital and analog flows are production-ready for third-generation 2nm class process, helping customers migrate to advanced Samsung Foundry nodes with speed and confidence. Through Synopsys and Samsung Foundry's continued DTCO initiatives, Synopsys Fusion Compiler™ on third-generation 2nm class process delivers measurable power and performance improvements validated with customers, compared to second-generation 2nm class process. 
  • Silicon-Based Power and Performance Improvements During Signoff with Certified Multiphysics Capabilities: New Synopsys PrimeShield™ Process Sensitivity Analysis and PVT Explorer support design-specific optimization and engineering change order (ECO) decisions during signoff, with demonstrated frequency improvement of up to 2.7% within 5% leakage current degradation respectively, informed by silicon feedback on 2nm class-based processes.1 In addition, Synopsys Totem-SC is a newly certified electromigration (EM) and IR drop analysis solution on second-generation 2nm and 4nm class processes improving silicon design power integrity and reliability.
  • AI-Powered Test Improves Efficiency and Quality of Designs: Synopsys and Samsung Foundry are applying silicon-proven methodologies to design for test (DFT) enablement and manufacturing test to reduce test cost and improve test quality for designs on advanced process nodes. For example, Synopsys TestMAX™ with AI-assisted automatic test pattern generation (ATPG) technologies (TSO.ai) validated and deployed in collaboration with Samsung Foundry teams, help reduce test patterns and test cycles up to 20% while preserving fault coverage on SoC and multi-die designs manufactured at Samsung Foundry. Additionally, physically aware tests and failure diagnosis at the die and multi-die level improve test quality and failure analysis turnaround time with results validated on silicon at Samsung Foundry.
  • Unified ExplorationtoSignoff Platform with Multiphysics Analysis Supporting Samsung's 3DIC Solution with Hybrid Copper Bonding Technology: Synopsys and Samsung Foundry are enabling scalable 3D multi-die designs through certified multiphysics signoff solutions delivered within Synopsys 3DIC Compiler, a unified exploration-to-signoff platform being validated on a Hybrid Copper Bonding (HCB) 3D test chip. The platform brings together planning, implementation, and multiphysics analysis to enable co-optimization across integrated compute, memory, and advanced packaging systems for Samsung's 3DIC solutions with HCB technology. By replacing manual, margin-based approaches with automated, AI-driven system optimization, the platform accelerates designer productivity while enhancing quality of results (QoR) for next-generation 3D AI designs.
  • Expanded IP Portfolio on Advanced and Automotive Nodes Decreases Design Integration Risk: Synopsys offers the industry's broadest portfolio of IP across Samsung Foundry's advanced processes from 14nm, 8nm, and 5nm class processes to the latest titles for 4nm and second-generation 2nm supporting a wide range of applications for segments including high-performance computing, consumer electronics, mobile devices, and edge AI, as well as automotive applications at 5nm and 2nm class processes. Synopsys' broad portfolio of interface IP—including UCIe, PCIe 7.0, 112G/224G, MIPI, LPDDR6, DDR5 MRDIMM Gen2 and USB4, — and foundation IP—including embedded memories, logic libraries, GPIOs, as well as security IP and Silicon Lifecycle Management (SLM)— are optimized through the companies' long-standing collaboration to deliver trusted, low-risk solutions tailored to Samsung's processes to support faster time to market.

SAFE Forum 2026 showcases the continued, deep collaboration between Synopsys and Samsung Foundry, driven by companies' shared commitment to co‑innovation and customer success at the most advanced nodes.

Follow Synopsys online for updates via our Newsroom, on LinkedIn, and on X.

Resources:

1 Compared to a previous version of Synopsys PrimeShield.

About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. Learn more at www.synopsys.com

© 2026 Synopsys, Inc. All rights reserved. Synopsys, Ansys, the Synopsys and Ansys logos, and other Synopsys trademarks are available at https://www.synopsys.com/company/legal/trademarks-brands.html. Other company or product names may be trademarks of their respective owners. 

Contacts
Media
Kelli Wheeler: kelliw@synopsys.com
Pete Smith: pete.smith@synopsys.com
corp-pr@synopsys.com 

Cision View original content to download multimedia:https://www.prnewswire.com/news-releases/synopsys-advances-power-and-performance-for-ai-and-multi-die-designs-on-latest-samsung-foundry-processes-at-safe-forum-2026-302784686.html

SOURCE Synopsys, Inc.

FAQ

What did Synopsys (SNPS) announce with Samsung Foundry at SAFE Forum 2026?

Synopsys announced expanded AI‑powered design, signoff, test, and IP enablement for Samsung Foundry’s latest advanced nodes. According to Synopsys, this includes new production‑ready flows, certified multiphysics signoff, silicon‑based test optimizations, and a broader interface IP portfolio spanning advanced and automotive process technologies.

How do Synopsys SNPS AI-powered flows support Samsung’s third-generation 2nm process?

Synopsys AI‑powered digital and analog flows are production‑ready for Samsung’s third‑generation 2nm class process. According to Synopsys, Fusion Compiler on this node delivers measurable power and performance improvements versus second‑generation 2nm, helping customers migrate to advanced Samsung nodes with greater speed and confidence.

What power and performance gains are reported from Synopsys PrimeShield on Samsung 2nm processes?

Synopsys reports frequency improvement of up to 2.7% with PrimeShield Process Sensitivity Analysis and PVT Explorer. According to Synopsys, this multiphysics‑driven optimization occurs during signoff within about 5% leakage current degradation, using silicon feedback from Samsung 2nm‑class processes to guide ECO and optimization decisions.

How does Synopsys TestMAX improve test efficiency for Samsung Foundry designs?

Synopsys TestMAX with AI‑assisted ATPG can reduce test patterns and cycles by up to 20%. According to Synopsys, this reduction is achieved while preserving fault coverage on SoC and multi‑die designs, using silicon‑validated methodologies deployed together with Samsung Foundry’s design and manufacturing test teams.

What 3DIC capabilities did Synopsys (SNPS) highlight for Samsung’s Hybrid Copper Bonding technology?

Synopsys is validating a unified 3DIC Compiler exploration‑to‑signoff platform on a Hybrid Copper Bonding 3D test chip. According to Synopsys, certified multiphysics signoff within this platform supports Samsung’s 3DIC solutions, enabling co‑optimization of compute, memory, and advanced packaging for next‑generation 3D AI designs.

Which interface IP does Synopsys offer for Samsung advanced and automotive nodes?

Synopsys offers interface IP such as UCIe, PCIe 7.0, 112G/224G, MIPI, LPDDR6, DDR5 MRDIMM Gen2, and USB4. According to Synopsys, this portfolio, plus foundation and security IP, spans 14nm to second‑generation 2nm nodes, including automotive applications at 5nm and 2nm processes.