Renesas Develops Circuit Technologies for 22-nm Embedded STT-MRAM with Faster Read and Write Performance for MCUs in IoT Applications
Renesas Electronics Corporation has developed advanced circuit technologies for a 22-nm embedded spin-transfer torque magnetoresistive random-access memory (STT-MRAM) test chip. This chip demonstrates 5.9 ns random read access and a 5.8 MB/s write throughput, enhancing performance for microcontroller units (MCUs). The technologies assist in achieving faster read/write operations, vital for IoT and AI applications. These advancements were showcased at the 2022 IEEE Symposium on VLSI in Hawaii, underscoring Renesas’ commitment to improving MCU efficiency and speed.
- Developed a 22-nm STT-MRAM test chip with 5.9 ns random read access.
- Achieved a write throughput of 5.8 MB/s, enhancing memory performance.
- Introduced fast read and write technologies, improving efficiency for microcontrollers.
- Potential to boost memory access speeds to exceed 100 MHz.
- MRAM has a smaller read margin than flash memory, limiting read speed.
- Challenges remain in decreasing system downtime for OTA updates.
Announced at 2022 Symposium on VLSI: Achieving 5.9 ns Random Read Access and 5.8 MB/s Write Throughput on Test Chip
Renesas STT-MRAM test chip with fast read and write operations (Graphic: Business Wire)
Renesas presented these achievements on
As the advances of IoT and AI technologies continue, microcontroller units (MCUs) used in endpoint devices are expected to deliver higher performance than ever, and therefore need to be fabricated with finer process nodes. MRAM fabricated in BEOL (Note 1) is advantageous compared to flash memory fabricated in FEOL (Note 2) for sub-22 nm processes because it is compatible with existing CMOS logic process technology and requires fewer additional mask layers. However, MRAM has a smaller read margin than flash memory, which degrades read speed. A large gap between the CPU operating frequency and the read frequency of the non-volatile memory is also a challenge since it can degrade MCU performance.
MRAM can also achieve shorter write time than flash memory because it requires no erase operation before write operation. However, further speed improvements are needed to shorten system downtime for over-the-air (OTA) updates required for endpoint devices and reduce costs for end product manufacturers in writing control codes for MCUs.
To address these challenges and respond to market demand for higher MCU performance, Renesas has developed the following new circuit technologies to achieve faster read and write operation in MRAM.
1. Fast Read Technology Employing High-Precision Sense Amplifier Circuit
MRAM uses memory cells including magnetic tunnel junction (MTJ) devices in which high and low-resistance states correspond to data values of 1 and 0 respectively to store information. A differential sense amplifier distinguishes between the two states by reading the voltage difference in discharge speed between the memory cell current and reference current. However, since the memory cell current difference between the 1 and 0 states is smaller for MRAM than for flash memory, the voltage difference read by the sense amplifier is smaller. Even if the discharge time is extended to wider voltage differences between the differential input nodes of the sense amplifier, both of the input nodes are susceptible to being completely discharged before securing a necessary voltage difference. This problem is particularly acute at high temperatures.
To resolve this issue, Renesas introduced a new technology utilizing capacitive coupling to boost the voltage level of the differential input nodes, allowing the differential amplifier to sense a voltage difference even when the memory cell current difference is small, achieving high-precision and fast read operation.
2. Fast Write Technology with Simultaneous Write Bit Number Optimization and Shortened Mode Transition Time
Following the high-speed write technologies for embedded STT-MRAM announced in
This technology divides up the areas to which write voltage is applied and, by inputting the write address before the write voltage setup, it selectively applies voltage only to the necessary area. This method reduces the parasitic capacitive load on the area where the voltage is applied during the write operation, reducing the voltage setup time. As a result, the mode transition time to write operation is reduced by approximately
Renesas continues to develop technologies aimed at the application of embedded MRAM technology in MCU products. These new technologies have the potential to dramatically boost memory access speed, which is currently a challenge with MRAM, to exceed 100 MHz, enabling higher-performance MCUs with embedded MRAM. Faster write speed will contribute to more efficient code writing to endpoint devices. Renesas is committed to further increasing capacity, speed, and power efficiency for MCUs to accommodate a range of new applications.
Notes
1. BEOL stands for “back end of line” and designates the latter portion of semiconductor fabrication from deposition of metal interconnect layers to completion.
2. FEOL stands for “front end of line” and designates the first portion of semiconductor fabrication where devices are patterned in the substrate and before the deposition of metal interconnect layers.
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