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Coherent to Showcase Silicon Photonics Based 1.6T Transceiver Modules Incorporating Next-Generation ICS for Low Power Consumption

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Coherent Corp. (NYSE: COHR) announced it will demonstrate its silicon photonics-based 1.6T-DR8 transceiver module at OFC 2025, featuring integration with Marvell's Ara 3nm optical digital signal processor (DSP). The demonstration showcases 200 Gbps electrical and optical interfaces.

The new transceiver, utilizing Marvell's 3nm DSP technology, aims to reduce power dissipation by over 20% compared to current 5nm DSPs in datacom transceivers. This improvement in energy efficiency is designed to lower operational costs and enable new AI server and networking architectures within data center power constraints.

The live demonstration will be available at Coherent's booth #1519 during OFC 2025 in San Francisco, April 1-3.

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Positive

  • 20% reduction in power dissipation through 3nm DSP technology integration
  • Advanced 200 Gbps electrical and optical interfaces implementation
  • Technology enables higher bandwidth AI applications while maintaining power constraints

Negative

  • None.

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-1.91% News Effect

On the day this news was published, COHR declined 1.91%, reflecting a mild negative market reaction.

Data tracked by StockTitan Argus on the day of publication.

SAXONBURG, Pa., March 31, 2025 (GLOBE NEWSWIRE) -- Coherent Corp. (NYSE: COHR), a global leader in photonics, will show a live demonstration of its silicon photonics-based 1.6T-DR8 transceiver module using a Marvell® Ara 3nm optical digital signal processor (DSP) at OFC 2025. This transceiver features 200 Gbps electrical and optical interfaces.

While the most advanced DSPs deployed in datacom transceivers today use 5nm node sizes, there is a constant push to an even smaller node size in order to minimize electrical power dissipation. Coherent’s transceiver in this demonstration uses Marvell Ara DSP, a 3nm 1.6T PAM4 optical DSP, which aims to reduce the power dissipation of 1.6T optical transceivers by over 20%.

Energy efficiency improvement reduces operational costs and enables new AI server and networking architectures to address the need for higher bandwidth and performance for AI workloads within the significant power constraints of the data center.

"Demonstrating this next generation of 1.6T transceivers highlights the versatility and robustness of our silicon photonics platform and highlights our strong drive to continually reducing power consumption," said Dr. Jack Xu, Vice President of Engineering for transceivers at Coherent. "As the industry transitions into the era of 200G optical lanes, we remain committed to reinforcing our market leadership by being at the forefront of innovation."

For additional information, please visit Coherent at booth #1519 during OFC 2025 in San Francisco, April 1-3.

About Coherent 

Coherent empowers market innovators to define the future through breakthrough technologies, from materials to systems. We deliver innovations that resonate with our customers in diversified applications for the industrial, communications, electronics, and instrumentation markets. Coherent has research and development, manufacturing, sales, service, and distribution facilities worldwide. For more information, please visit us at coherent.com.  

Media Contact: 

innovations@coherent.com 

  



FAQ

What power efficiency improvement does Coherent's (COHR) new 1.6T transceiver achieve?

The new 1.6T transceiver aims to reduce power dissipation by over 20% using Marvell's 3nm DSP technology compared to current 5nm DSPs.

What are the interface specifications of Coherent's (COHR) new 1.6T-DR8 transceiver?

The transceiver features 200 Gbps electrical and optical interfaces.

When and where will Coherent (COHR) demonstrate its new 1.6T transceiver?

The demonstration will take place at OFC 2025 in San Francisco, April 1-3, at booth #1519.

How does Coherent's (COHR) new transceiver technology benefit AI applications?

The improved energy efficiency enables new AI server and networking architectures to achieve higher bandwidth and performance within data center power constraints.
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