Cadence Expands System IP Portfolio with Network on Chip to Optimize Electronic System Connectivity

Rhea-AI Summary

Cadence Design Systems has expanded its system IP portfolio with the Cadence Janus Network-on-Chip (NoC). This addition aims to address the increased complexity and data delivery challenges within and between silicon components in larger SoCs and disaggregated multi-chip systems. The Janus NoC enhances power, performance, and area (PPA) targets, reducing latency and freeing engineering resources for SoC differentiation. Leveraging Cadence's Tensilica RTL tools, the NoC allows for extensive simulation and emulation, aiding in architectural exploration and mitigating routing congestion and timing issues. The Janus NoC will be available in July 2024.

Positive

• Cadence expands its system IP portfolio with the Janus NoC to address SoC complexity.
• Janus NoC enhances power, performance, and area (PPA) with reduced latency.
• Enables quicker achievement of PPA targets, freeing up engineering resources.
• Leverages Cadence's proven Tensilica RTL generation tools for NoC design.
• Supports architectural exploration through extensive simulation and emulation capabilities.
• Reduces design complexity with built-in power management and clock domain crossing.
• Scalable architecture allows for future reuse in multi-chip systems.

Negative

• Availability of Janus NoC is delayed until July 2024.

Financial Analyst

Cadence's expansion of its system IP portfolio with the new Janus Network-on-Chip (NoC) is a strategic move that could have significant implications for its financial performance. The Janus NoC aims to optimize power, performance and area (PPA) in system-on-chip (SoC) designs, which is critical for addressing the escalating compute demands of modern electronics.

From a financial perspective, this innovation could drive increased revenue through both direct sales and enhanced customer satisfaction. The reduced design complexity and faster time-to-market offered by the Janus NoC may attract more clients, leading to a potential growth in market share. Moreover, the ability to mitigate routing congestion and timing issues can help customers achieve efficiencies, resulting in repeat business and long-term partnerships.

Investors should note that this product aligns with the company's strategy to evolve from an IP provider to an SoC design partner, which can be seen as a move to capture a larger portion of the value chain. The availability in July 2024 sets a clear timeline for when Cadence might start realizing revenue from this product, although it may take several quarters post-release for the financial impact to become evident in earnings reports.

Tech Expert

The introduction of the Janus Network-on-Chip (NoC) by Cadence is a testament to the company's commitment to innovation in the semiconductor sector. The NoC addresses important issues in SoC designs like routing congestion and timing, which can significantly affect the overall system performance. The advanced GUI for configuration and the compatibility with industry-standard interfaces like AXI4 and AHB ensures that this new product is both user-friendly and versatile.

One notable feature is the built-in power management and the clock domain crossing, which help reduce design complexity and risk. These features are important as they allow design teams to focus on differentiating their silicon rather than troubleshooting connectivity issues. Additionally, the NoC's ability to enable early architectural exploration and quick validation of PPA results is likely to be a significant time-saver for engineers, leading to faster product development cycles.

The scalability of the architecture also means that it can be adapted for future innovations, thus offering lasting value. This is particularly important in an industry where technology evolves rapidly and companies must continuously innovate to stay competitive.

Market Research Analyst

From a market standpoint, the introduction of the Janus NoC by Cadence could have meaningful implications for the competitive landscape. As the demand for high-performance computing continues to grow, the need for efficient interconnect solutions within SoCs has become more critical. The Janus NoC addresses this by offering optimized PPA outcomes, which are essential for modern electronics, particularly in sectors like AI, IoT and automotive.

Cadence's strategic move to expand its portfolio is likely to position the company more favorably against competitors like Synopsys and ARM, who also offer interconnect solutions. By leveraging its well-established Tensilica RTL generation tools and comprehensive simulation and emulation capabilities, Cadence can provide a more integrated solution, potentially giving it a competitive edge.

Customers in the semiconductor industry are continually looking for ways to reduce time-to-market and minimize design risks. The Janus NoC’s features such as high-speed communication with minimal latency and easy NoC configuration make it an attractive option. This could lead to a higher adoption rate, ultimately benefiting Cadence's market position and driving growth in both revenue and customer base.

Cadence Janus NoC enables design teams to achieve better PPA faster and with lower risk, freeing up valuable engineering resources for SoC differentiation

SAN JOSE, Calif.--(BUSINESS WIRE)-- Cadence Design Systems, Inc. (Nasdaq: CDNS) today expanded its system IP portfolio with the addition of the Cadence^® Janus^™ Network-on-Chip (NoC). As larger, more complex SoCs and disaggregated multi-chip systems proliferate to accommodate today’s escalating compute demands, data delivery within and between silicon components has become increasingly challenging—impacting power, performance and area (PPA). The Cadence Janus NoC manages these simultaneous high-speed communications efficiently with minimal latency, enabling customers to achieve their PPA targets faster and with lower risk.

The Cadence Janus Network-on-Chip (NoC) efficiently manages simultaneous high-speed communications within and between silicon components with minimal latency. This enables customers to achieve their power, performance and area (PPA) targets faster and with lower risk, freeing up valuable engineering resources for SoC differentiation. (Graphic: Business Wire)

“Cadence is an established leader in IP and design quality, and we continue to invest in our foundational interface and processor IP, system IP, software and design services capabilities to enable our customers to develop differentiated and disaggregated designs,” said Boyd Phelps, senior vice president and general manager of the Silicon Solutions Group at Cadence. “The addition of the Cadence Janus NoC to our growing system IP portfolio is a key milestone in this strategy. Our evolution from an IP provider to an SoC design partner delivers greater value to our customers, empowering them to focus valuable engineering resources on differentiating their silicon.”

The Cadence Janus NoC leverages Cadence’s legacy of trusted and time-proven Tensilica^® RTL generation tools. Customers can utilize Cadence’s extensive portfolio of software and hardware for simulation and emulation of their NoC and gain deep insights into its performance using Cadence’s System Performance Analysis tool (SPA). By enabling architectural exploration, this flow results in the best NoC design to meet product needs. The NoC leverages Cadence’s well-established leadership in IP and quality, backed by industry-leading customer satisfaction for technical support.

The Cadence Janus NoC mitigates the routing congestion and timing issues associated with today’s complex SoC interconnects, which often don’t become apparent until physical implementation. Addressing the most pressing needs today, Cadence’s first-generation NoC provides a platform for future innovations, such as support for industry-standard memory and I/O coherence protocols. Current features and benefits include:

• Easy to use: Cadence’s powerful, state-of-the-art GUI enables easy NoC configuration ranging from small subsystems to full SoCs and future multi-chip systems.
• Accelerated time to market: PPA-optimized RTL enables SoC designers to achieve their bandwidth and latency goals. Packetized messages enable higher utilization of wires, reducing wire count and timing closure challenges.
• Lower risk: The NoC’s built-in power management, clock domain crossing and width matching reduce design complexity.
• Quick turnaround: Cadence’s extensive simulation and emulation capabilities enable early architectural exploration, allowing quick validation of PPA results to ensure the configuration meets design requirements.
• Scalable architecture: Customers can design a subsystem and reuse it in a full SoC context of the NoC, allowing future reuse in a multi-chip system.
• Flexible: The NoC is compatible with any IP with an industry-standard interface, including AXI4 and AHB.

“We are pleased that Cadence is expanding its IP portfolio by investing in system-level solutions,” said Suk Lee, VP and GM, Ecosystem Technology Office at Intel Foundry. “As a NoC is vital for almost any subsystem in today’s SoCs, we support Cadence’s initiatives in developing their NoC and look forward to them continuing to expand their IP offering going forward.”

Availability and Related Resources

The Cadence Janus NoC will be available in July 2024.

• Product brief
• White paper
• Webpage

About Cadence

Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For 10 years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.

Category: Featured

View source version on businesswire.com: https://www.businesswire.com/news/home/20240625350157/en/

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Source: Cadence Design Systems, Inc.

FAQ

What is the Cadence Janus Network-on-Chip (NoC)?

The Cadence Janus Network-on-Chip (NoC) is a system IP component designed to manage high-speed communications within and between silicon components, enhancing power, performance, and area (PPA) targets with minimal latency.

How does the Janus NoC benefit SoC design?

The Janus NoC reduces design complexity and latency, enabling quicker achievement of PPA targets and freeing up engineering resources for SoC differentiation.

When will the Cadence Janus NoC be available?

The Cadence Janus NoC will be available in July 2024.

What tools does the Janus NoC leverage?

The Janus NoC leverages Cadence’s legacy Tensilica RTL generation tools and offers extensive simulation and emulation capabilities to aid in architectural exploration.

What are the key features of the Cadence Janus NoC?

Key features include easy NoC configuration, PPA-optimized RTL, built-in power management, clock domain crossing, and scalable architecture for future reuse in multi-chip systems.

Why is Cadence expanding its system IP portfolio with the Janus NoC?

Cadence is expanding its system IP portfolio to address the increasing complexity and data delivery challenges of larger SoCs and disaggregated multi-chip systems, enhancing PPA targets and reducing latency.