Cadence Demonstrates IP Test Silicon for PCI Express 6.0 Specification on TSMC N5 Process

Rhea-AI Summary

Cadence Design Systems (CDNS) announces the availability of PCIe 6.0 IP on TSMC's N5 process, featuring a DSP-based PHY and advanced controller for enhanced performance in hyperscale computing and 5G applications. The PCIe 6.0 PHY test chip showcased excellent electrical performance and low jitter, accommodating harsh conditions. The controller supports high throughput with low latency, achieving 128Gbps bandwidth. Early adopters can access design kits now, with a test chip tape-out completed in July 2021. This supports Cadence's Intelligent System Design strategy, affirming its position as a leader in electronic design.

Positive

• Launch of PCIe 6.0 IP on TSMC N5 process enhances Cadence's product offerings.
• Successful test chip silicon demonstrated excellent electrical performance.
• High link throughput and low latency from the new controller IP improve performance metrics.
• Early adoption indicates market confidence and potential revenue growth.

Negative

• None.

Design kits now available for early adopters

SAN JOSE, Calif.--(BUSINESS WIRE)-- Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the immediate availability of Cadence^® IP supporting the PCI Express^® (PCIe^®) 6.0 specification on the TSMC N5 process. The Cadence IP for PCIe 6.0 consists of a high-performance DSP-based PHY and a feature-rich companion controller to deliver the optimized performance and throughput for next-generation applications in hyperscale computing and 5G communications, including networking, emerging memory and storage. Early adopters of Cadence IP for PCIe 6.0 can access design kits now.

The 5nm PCIe 6.0 PHY test chip silicon from Cadence demonstrated excellent electrical performance across all PCIe rates. The PAM4/NRZ dual-mode transmitter delivered optimal signal integrity, symmetry and linearity with extremely low jitter. The DSP-based receiver demonstrated robust data recovery capabilities while withstanding harsh signal impairments and channel loss in excess of 35dB at 64GT/s. In addition, the advanced DSP core in the PHY provides continuous background adaptation to monitor and compensate for the signal fluctuations induced by environmental factors, achieving enhanced reliability.

The Cadence controller IP for PCIe 6.0 is designed to provide the highest link throughput and utilization while operating with extremely low latency. The highly scalable multi-packet processing architecture supports up to 1024-bit wide data path in x16 configuration while operating at 1GHz to achieve maximum aggregate bandwidth of 128Gbps. The feature-rich controller IP supports all the new PCIe 6.0 features, including PAM4 signaling, Forward Error Correction (FEC), FLIT Encoding and L0p power state while retaining full backward compatibility.

A PCIe 6.0 subsystem test chip was taped out on TSMC N5 in July 2021. This subsystem test chip integrated the second-generation power, performance and area (PPA)-optimized PCIe 6.0 PHY together with the PCIe 6.0 controller. This subsystem test chip enables Cadence to validate PCIe 6.0 PHY and controller functions at the system level and perform rigorous compliance and stress tests to ensure universal interoperability and reliability.

“We work closely with Cadence, our long-standing ecosystem partner, to enable next-generation designs benefiting from the significant power, performance and area improvements of our advanced technologies,” said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. “This collaborative effort combining Cadence’s leading IP solution with TSMC’s 5nm technology will help our mutual customers meet the most challenging power and performance requirements and quickly launch their differentiated product innovations.”

“Early adopters have already started exploring with the new PCIe6 specification, and we are looking forward to seeing them achieve positive results with TSMC and Cadence technologies,” said Sanjive Agarwala, corporate vice president and general manager of the IP Group at Cadence. “We’ve been deploying PAM4-based IP since 2019 when we introduced our first-generation 112G-LR SerDes IP, and our vast expertise in PAM4 technology plus our strong collaboration with TSMC provides a robust foundation for success with our PCIe6 products.”

The Cadence IP for the PCIe 6.0 specification supports the company’s Intelligent System Design^™ strategy, which enables SoC design excellence. Cadence’s comprehensive portfolio of design IP solutions for TSMC’s advanced processes also includes 112G, 56G, die-to-die (D2D) and advanced memory IP solutions. For more information on the Cadence IP for PCIe 6.0 specification, please visit www.cadence.com/go/pcie6pr.

About Cadence

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications, including consumer, hyperscale computing, 5G communications, automotive, mobile, aerospace, industrial and healthcare. For seven years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.

© 2021 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. PCI Express and PCIe are registered trademarks of PCI-SIG. All other trademarks are the property of their respective owners.

Category: Featured

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For more information, please contact:

Cadence Newsroom

408-944-7039

newsroom@cadence.com

Source: Cadence Design Systems, Inc.

FAQ

What new product did Cadence Design Systems launch regarding PCIe 6.0?

Cadence launched PCIe 6.0 IP supporting the specification on TSMC's N5 process.

What are the key features of Cadence's PCIe 6.0 IP?

The PCIe 6.0 IP features a DSP-based PHY and an advanced controller with high throughput and low latency.

When was the PCIe 6.0 subsystem test chip taped out?

The PCIe 6.0 subsystem test chip was taped out in July 2021.

What applications are targeted by the new PCIe 6.0 IP from Cadence?

The PCIe 6.0 IP targets hyperscale computing and 5G communication applications.

How does the new PCIe 6.0 technology support Cadence's business strategy?

The PCIe 6.0 technology supports Cadence's Intelligent System Design strategy, enhancing their design IP portfolio.