Cadence Custom Design Migration Flow Accelerates Adoption of TSMC N3E and N2 Process Technologies
Cadence Design Systems (CDNS) has launched a node-to-node design migration flow within its Virtuoso Design Platform, facilitating automated migration of integrated circuit designs to TSMC's latest process technologies like N3E and N2. This collaboration has yielded significant efficiency gains, with users reporting a 2.5X reduction in design migration time compared to manual methods. The platform's capabilities include automatic migration of schematic elements and optimization to meet design specifications.
Cadence's enhanced process development kits (PDKs) support this migration, which is critical as clients increasingly seek to leverage advanced nodes for better performance and lower power consumption. The advancements aim to streamline the migration process, ultimately reducing time-to-market for complex designs.
- Launch of automated node-to-node migration technology enhances design efficiency.
- Users experience a 2.5X reduction in migration time, improving productivity.
- Collaboration with TSMC ensures compatibility with advanced technologies, aiding customers in adopting new nodes.
- None.
- Cadence Virtuoso Design Platform automates migration of IC designs to TSMC’s latest process technologies
- New generative design technology delivers a 2.5X reduction in design migration time
- Corresponding PDKs support easy node-to-node design and layout migration
The Virtuoso Design Platform automatically migrates schematic cells, parameters, pins and wiring from one TSMC process node to another. The Virtuoso ADE Product Suite’s simulation and circuit optimization environment then tunes and optimizes the new schematic to ensure the design achieves all required specifications and measurements.
Cadence and TSMC customers can then automatically recognize and extract groups of devices in an existing layout and apply them to similar groups in the new layout, thanks to the Virtuoso Layout Suite’s generative design technology using templates, TSMC’s analog-mapping and routing technologies in the Virtuoso Design Platform.
“As application requirements grow, many TSMC customers are looking to migrate legacy IC designs to our more advanced nodes, such as N3E and N2, to take full advantage of higher performance and lower power benefits of the latest TSMC advanced technologies,” said Dan Kochpatcharin, head of the
“Through this latest collaboration with TSMC, our joint customers benefit from our advanced technologies that make custom/analog migration simpler and far less time-consuming,” said
The Cadence Virtuoso Design Platform supports the Cadence Intelligent System Design™ strategy, enabling system-on-chip (SoC) design excellence. To learn more about the Virtuoso Design Platform, please visit www.cadence.com/go/virtuosomrgrationN3EN2pr.
About Cadence
Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For nine years in a row,
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