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Cadence Design Systems Inc (CDNS) provides critical electronic design automation (EDA) software and semiconductor intellectual property solutions powering modern chip development. This news hub offers investors and industry professionals centralized access to official announcements and market-relevant updates.
Track earnings reports, product launches, and strategic partnerships shaping the EDA landscape. Our curated collection ensures timely access to developments impacting semiconductor design innovation across automotive, AI hardware, and IoT sectors.
Discover how Cadence's tools in digital verification, custom IP blocks, and system-level integration address evolving industry challenges. Bookmark this page for streamlined monitoring of operational milestones and technology advancements directly from the source.
Cadence (CDNS) has strengthened its partnership with TSMC to accelerate 3D-IC and advanced-node technology development through certified design flows and silicon-proven IP. The collaboration includes certification for TSMC's N2P and A16 technologies, with initial work on A14 technology.
Key developments include:
- TSMC9000 pre-silicon-certified DDR5 12.8G IP for N2P
- Certified IP for TSMC's N5A and N3A processes targeting automotive applications
- Expansion of design IP portfolio with HBM3E 9.6G in N5/N4P and pre-silicon HBM3E 10.4G in N3P
- Enhanced Integrity 3D-IC Platform with improved quality of results and 3DIC full flow QC
The partnership focuses on AI chip design innovation, automotive solutions for ADAS and autonomous driving, and advancement in 3DFabric solutions for chiplet design and packaging.
Cadence (CDNS) has unveiled the industry's first DDR5 12.8Gbps MRDIMM Gen2 memory IP system solution on TSMC N3 process, targeting enterprise and data center applications with AI processing demands. The solution features a doubled bandwidth compared to current DDR5 6400Mbps DRAM parts.
The new memory IP system includes a PHY and high-performance controller, offering ultra-low latency encryption and advanced RAS features. The solution has been validated in hardware using the latest Gen2 MRDIMMs and is designed to enable advanced SoCs and chiplets with flexible floorplan options.
The technology has already secured multiple engagements with leading AI, HPC, and data center customers. The solution is compatible with Micron's 1γ-based DRAM and Montage's MRCD02/MDB02 chips for MRDIMMs, positioning it as a key enabler for next-generation server and data center products.
Cadence (CDNS) has unveiled the industry's fastest HBM4 12.8Gbps memory IP solution, designed for next-generation AI training and HPC hardware systems. The solution, compatible with JEDEC specification JESD270-4, doubles the memory bandwidth compared to previous HBM3E IP products.
Key features include:
- 20% greater power efficiency per bit
- 50% better area efficiency
- Double the number of I/Os for higher bandwidth
- 12.8Gbps data rate exceeding HBM4 DRAM device speeds by 60%
The solution includes a PHY available as a drop-in hardened macro in TSMC N3 and N2 technology nodes, and a controller provided as a soft RTL macro. The package includes comprehensive deliverables, reference interposer design, and LabStation software for rapid SoC post-silicon lab bring-up.
Cadence (CDNS) has announced a definitive agreement to acquire Arm's Artisan foundation IP business, which includes standard cell libraries, memory compilers, and general-purpose I/Os optimized for advanced process nodes. The acquisition will enhance Cadence's design IP portfolio, complementing its existing protocol, interface, memory interface, SerDes IP, and embedded security IP offerings from the pending Secure-IC acquisition.
The transaction involves an asset purchase agreement with a concurrent technology license agreement. Cadence will acquire a skilled engineering team to accelerate IP product development. The deal is expected to close in Q3 2025, subject to regulatory approvals and closing conditions, and is anticipated to be immaterial to revenue and earnings this year.
Cadence (CDNS) has scheduled its first quarter 2025 financial results webcast for Monday, April 28, 2025, at 2:00 p.m. Pacific Time. The presentation will feature Dr. Anirudh Devgan, president and CEO, alongside John Wall, senior vice president and CFO.
The webcast recording will be accessible online at cadence.com/cadence/investor_relations from 5:00 p.m. Pacific Time on April 28 until June 16, 2025, at 5:00 p.m. Pacific Time.
Cadence (CDNS) has been named one of the Fortune 100 Best Companies to Work For in 2025, securing the 11th position. This marks the company's 11th appearance on this prestigious list, highlighting its commitment to workplace excellence.
The recognition is based on Great Place To Work's Trust Index™ Survey, incorporating feedback from over 1.3 million U.S. employees across 60 criteria. Notable statistics show that 93% of employees are proud to work at Cadence, and 90% feel they make a difference.
CEO Dr. Anirudh Devgan emphasized Cadence's culture of trust, integrity, and commitment to excellence. The company is recognized for delivering AI-driven solutions across industries including autonomous driving, hyperscale computing, and life sciences. Cadence has also received Great Place To Work recognition in 13 countries, including Brazil, Canada, China, and was named a World's Best Workplace with regional recognition in Asia and Europe.
Cadence (CDNS) announced an expanded multi-year collaboration with NVIDIA, focusing on accelerated computing and agentic AI integration. The partnership highlights significant performance improvements using NVIDIA's latest Blackwell architecture, including:
- Computational fluid dynamics simulation time reduced by up to 80X
- Cadence Spectre X Simulator accelerated by up to 10X
- 3D-IC design and analysis acceleration up to 7X
The collaboration features the integration of Cadence JedAI Platform with NVIDIA's NeMo framework and the new Llama Nemotron Reasoning Model. Additionally, Cadence is among the first adopters of NVIDIA Omniverse Blueprint for AI factory digital twins, enabling efficient data center design and operation through the integration of Omniverse Viewport, Allegro X Design Platform, and Reality Digital Twin Platform.
Cadence Design Systems (Nasdaq: CDNS) has announced that President and CEO Anirudh Devgan will participate in a fireside chat at the Morgan Stanley Technology, Media & Telecom Conference in San Francisco. The presentation is scheduled for March 5, 2025, at 2:35 p.m. PST.
The event will be accessible through a live webcast on the company's website at cadence.com/cadence/investor_relations. For those unable to attend live, the presentation will remain available for replay on the Cadence website for 180 days following the event.
Cadence Design Systems (CDNS) reported strong Q4 and fiscal year 2024 results, with Q4 revenue reaching $1.356 billion, up from $1.069 billion in Q4 2023. The company achieved a record backlog of $6.8 billion and current remaining performance obligations (cRPO) of $3.4 billion.
Q4 highlights include GAAP operating margin of 33.7% and non-GAAP operating margin of 46.0%. For the full year 2024, revenue grew 13.5% to $4.641 billion with a non-GAAP operating margin of 42.5%. The company's IP business grew 28% year-over-year in Q4, while Core EDA grew 15%.
Looking ahead to 2025, Cadence expects revenue between $5.14-$5.22 billion and non-GAAP diluted EPS of $6.65-$6.75.
MediaTek has adopted Cadence's AI-driven Virtuoso Studio and Spectre X Simulator on NVIDIA's platform for its 2nm designs, achieving significant productivity improvements. The implementation has resulted in a 30% productivity gain in their design flow compared to previous versions.
Key achievements include up to 6X greater performance using Spectre X Simulator on NVIDIA Hopper GPUs while maintaining accuracy, and an additional 30% design productivity improvement through Virtuoso Studio's layout routing and placement tools. MediaTek has integrated its own AI-powered optimization algorithm using the Virtuoso ADE Suite for future product development.
The collaboration enables MediaTek to meet aggressive performance and turnaround time requirements for 2nm high-speed analog IP development, with enhanced throughput and efficiency through comprehensive automation features.
