ASE announces FOCoS advancements under the VIPack™ Platform
Advanced Semiconductor Engineering (ASE), a leader in semiconductor manufacturing, has launched the industry's first Fan-Out Chip on Substrate (FOCoS) packaging solutions: FOCoS-CF and FOCoS-CL. These innovations enhance performance for High Performance Computing (HPC) and artificial intelligence applications by improving chip integration and electrical performance. FOCoS-CF features encapsulant-separated redistribution layers for better signal integrity, and FOCoS-CL optimizes High Bandwidth Memory (HBM) integration. These technologies aim to meet the growing market demand for high density and low latency connections.
- Launch of innovative FOCoS-CF and FOCoS-CL packaging solutions.
- Improved chip integration capabilities enhance electrical performance.
- Addresses market demand for High Bandwidth Memory in HPC and AI applications.
- Potential for cost efficiencies and yield improvements through advanced packaging technology.
- None.
The growing demand for high density, high speed, and low latency of chip-to-chip interconnect is driving a new level of packaging innovations such as FOCoS-CF and FOCoS-CL. This combined FOCoS-CF and FOCoS-CL portfolio addresses the limitations of traditional flip-chip packages where a single SoC is assembled on a substrate by enabling multi-chip and chiplet integration where two or more chips can be reconstituted into a fan-out module and then assembled on a substrate. Encapsulant-separated RDL is a chip first technology that helps to address some of the die placement and design rule related issues seen with the traditional reconstituted wafer process technology.
FOCoS-CF using encapsulant-separated RDL enables improved Chip Package Interaction (CPI), lessened mechanical stress risk over the chip edge at RDL, and better high frequency signal integrity. There are also advanced design rule improvements that enable a higher IO density by up to 10x existing by reducing pad pitches, while creating heterogeneous integration opportunities across chips from varying nodes and different fabs.
Data shows that FOCoS-CL is particularly effective for High Bandwidth Memory (HBM) integration, a technology area of growing significance given its ability to optimize power efficiency and space savings. As demand for HBM continues to grow within the HPC, server, and networking markets, FOCoS-CL innovation delivers crucial performance and footprint advantages.
Heterogeneous integration through advanced packaging technology enables chiplet integration with separate designs and different manufacturing process nodes within a single package. It provides advancement for greater system intelligence, better connectivity, and higher performance at a more manageable cost while delivering a compelling value proposition for yield improvement and IP reuse. ASE’s FOCoS portfolio including FOCoS-CF using encapsulant-separated RDL and FOCoS-CL, aligns with market demand as both solutions provide different chips and flip-chip devices to be packaged on a high pin count BGA substrate, allowing the system and package architects to design the optimal package integration solution for their product strategy, value proposition, and time-to-market.
FOCoS packaging technology enables chiplet integration with multiple RDL interconnects up to five layers, a smaller RDL L/S of 1.5/1.5µm, and a large fan-out module size of 34x50mm2. It also provides a wide portfolio integration, such as an application-specific integrated circuit (ASIC) with high-bandwidth memory (HBM) and ASIC with Serdes across many segments of HPC, networking, artificial intelligence/machine learning (AI/ML) and the cloud. Furthermore, FOCoS has demonstrated better electrical performance and lower cost than 2.5D Si TSV because of the elimination of the Si interposer along with reducing parasitic capacitance.
“The magic of FOCoS-CF and FOCoS-CL is that we are able to optimize integration possibilities by scaling the electrical connectivity in fan-out to interconnect multiple different chips, simultaneously achieving both heterogeneous and homogeneous integration where chips are split up and combined within a fan-out package,’” said Dr.
“The semiconductor industry is trending towards chiplet-based architectures that rely on transformative packaging innovations to deliver critical power and performance requirements,” commented
ASE’s FOCoS-CF and FOCoS-CL technologies feature within VIPack™, a scalable platform available now that is expanding in alignment with industry roadmaps.
Supporting resources
- For more about FOCoS-CF and FOCoS-CL, please visit: https://ase.aseglobal.com/public/en/technology/focos.html
- For more about VIPack™, please visit: ase.aseglobal.com/en/VIPack
- Follow us on our LinkedIn page for targeted updates and announcements @aseglobal
- Follow us on Twitter @aseglobal
About
View source version on businesswire.com: https://www.businesswire.com/news/home/20221103005073/en/
Source:
FAQ
What is the significance of ASE's FOCoS-CF and FOCoS-CL packaging solutions?
When were ASE's FOCoS technologies announced?
What benefits do the FOCoS solutions provide for semiconductor packaging?
What markets are expected to benefit from ASE's FOCoS technology?
How does FOCoS technology improve chip-to-chip interconnect performance?
