Synopsys Announces Industry's First CXL 2.0 VIP Solution for Breakthrough SoC Performance

Rhea-AI Summary

Synopsys, Inc. (Nasdaq: SNPS) launched the first Verification IP for Compute Express Link (CXL) 2.0, enhancing performance for data-intensive system-on-chips (SoCs). This new technology supports high-speed communication between CPUs and accelerators, built on the PCI Express infrastructure. Offering next-generation SystemVerilog architecture, the VIP accelerates integration and simulation performance. CXL 2.0 introduces advanced features like switching, security, and manageability enhancements. Both the Verification IP and DesignWare CXL IP solutions are available now.

Positive

• Launch of industry's first CXL 2.0 Verification IP enhances Synopsys' market positioning.
• Next-generation architecture improves simulation performance and integration.
• Supports emerging applications with high data throughput, vital in AI and cloud computing.
• Collaboration with standards organizations boosts adoption of CXL technology.

Negative

• None.

MOUNTAIN VIEW, Calif., Nov. 10, 2020 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today announced the availability of the industry's first Verification IP (VIP) for Compute Express Link^™ (CXL^™) 2.0 designed for breakthrough performance in data-intensive system-on-chips (SoCs). CXL is the next-generation open standard interconnect that enables an ecosystem for high-speed communication between the CPU and workload accelerators, such as GPUs, FPGAs and other purpose-built accelerator solutions, as well as memory expansion devices. The technology is built upon the well-established PCI Express^® infrastructure, leveraging the PCI Express 5.0 physical and electrical interface.

Synopsys VIP for CXL uses next-generation native SystemVerilog Universal Verification Methodology (UVM) architecture that enables ease of integration within existing verification environments and speeds up simulation performance allowing users to run greater number of tests and accelerate time to first test. VIP for CXL is natively integrated with Synopsys Verdi^® Protocol and Performance Analyzer and includes built-in coverage and verification plans for faster verification closure. In addition, Synopsys' silicon-proven DesignWare^® CXL IP delivers a x16 link for maximum bandwidth with low latency, supporting all three CXL protocols (CXL.io, CXL.cache, CXL.mem) and device types to meet specific application requirements.

"Synopsys' cache coherency verification IP portfolio, including CXL 2.0, CXL 1.1 and CCIX, enables support of emerging applications with massive data throughput requirements," said Vikas Gautam, Vice President of R&D for the Synopsys Verification Group. "Our growing portfolio of industry-first verification IP and close collaborations with standards organizations and memory vendors enable designers to adopt and integrate the latest interconnect technologies rapidly."

"The advancement of CXL as an open standard interconnect technology to accelerate next generation data center performance is our singular focus," said Jim Pappas, Chairman at CXL Consortium. "We appreciate Synopsys' support of CXL Consortium to help advance the adoption of CXL technology."

"Bringing to market the next major interconnect advancement for data intensive applications, such as artificial intelligence, memory expansion, and cloud computing requires a robust ecosystem," said Dr. Debendra Das Sharma, Intel Fellow and Director I/O Technologies and Standards. "Collaborating with industry-leaders like Synopsys to advance CXL propels the industry forward and enables our customers to meet the performance and data connectivity requirements of their SoCs."

The CXL 2.0 protocol comes with an increased fan-out, pooling feature set for both physical layer and application layers. New features supported by CXL 2.0 are:

-  CXL switching and support for multiple logical devices (MLD)

-  IDE (security) for both CXL.io & CXL.cache/mem

-  Ability to negotiate CXL 2.0 devices during APN phase and hot plug, CXL enumeration to view CXL device as PCI Express endpoint

-  Updates for system level manageability through QoS telemetry, function level reset, global persistent flush, memory interleaving and compliance test assertions

Availability & Additional Resources

Synopsys VC VIP for CXL 2.0/1.1 is available today. DesignWare CXL IP Solution is also available now. For more information, visit VC Verification IP for CXL and DesignWare CXL IP

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software^™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15^th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing application that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.

Compute Express Link and CXL are trademarks of the CXL Consortium.

Editorial Contacts:
Simone Souza
Synopsys, Inc.
650-584-6454
simone@synopsys.com

View original content:http://www.prnewswire.com/news-releases/synopsys-announces-industrys-first-cxl-2-0-vip-solution-for-breakthrough-soc-performance-301169680.html

SOURCE Synopsys, Inc.

FAQ

What is the significance of Synopsys' CXL 2.0 Verification IP for SNPS?

The launch positions Synopsys as a leader in providing essential tools for high-performance data-intensive SoC applications.

When was the CXL 2.0 Verification IP announced by Synopsys?

It was announced on November 10, 2020.

What technologies does Synopsys' CXL 2.0 Verification IP support?

It supports high-speed communication between CPUs, GPUs, and other accelerators, enhancing data center performance.