Rambus Delivers 112G XSR/USR PHY on TSMC 7nm Process for Chiplets and Co-Packaged Optics in Networking and Data Center

Rhea-AI Summary

Rambus Inc. (NASDAQ: RMBS) has expanded its high-speed interface IP portfolio with the introduction of the 112G XSR/USR PHY on TSMC's 7nm process. This solution enhances power and area efficiency, addressing the growing demand for chiplet architectures in data centers, networking, 5G, HPC, and AI/ML applications. The 112G XSR/USR PHY surpasses CEI-112G XSR specifications, supporting NRZ and PAM-4 signaling. Available for licensing, it enables advanced designs and connectivity solutions for next-gen ASICs and SoCs.

Positive

• Launch of 112G XSR/USR PHY enhances product portfolio.
• Demonstrated high efficiency with sub-picojoule per bit performance.
• Addresses growing market demand for chiplet architectures.

Negative

• None.

SUNNYVALE, Calif., June 17, 2020 /PRNewswire/ -- Rambus Inc. (NASDAQ: RMBS), a premier silicon IP and chip provider making data faster and safer, today announced it has expanded its portfolio of high-speed interface IP on TSMC's industry-leading 7nm process with the addition of its silicon-demonstrated 112G XSR/USR PHY. Offering unmatched power and area efficiency for next-generation applications, the 112G XSR/USR PHY is a critical enabler of chiplet and CPO architectures for data center, networking, 5G, HPC and AI/ML applications.

"Chiplets are already entering mainstream markets to enable cost-effective, high-performance products and to maintain signal integrity across variable physical distances," said Shane Rau, research vice president, computing semiconductors at IDC. "SerDes PHYs at advanced process nodes, like the 7nm 112G XSR, enable that speed and signal integrity."

The accelerated trend of disaggregation of large SoCs into multiple smaller chiplets demands faster time to market, yield improvement and design flexibility. The Rambus 112G XSR/USR PHY is a critical enabler of the D2D and D2OE interconnects for chiplet architectures. Implemented on TSMC's advanced process technology, this chiplet connectivity solution has been demonstrated in silicon to exceed the challenging reach/BER performance of the CEI-112G XSR specification, and supports NRZ and PAM-4 signaling at various data rates for maximum design flexibility.

"We're pleased with the availability of Rambus' PHY on our N7 process technology to address the growing market need for low-power, high-performance chiplet architectures," said Suk Lee, senior director of the Design Infrastructure Management Division at TSMC. "Our ongoing partnership with Rambus ensures that designers can meet next-generation requirements for performance and power efficiency in computing, AI/ML and networking using TSMC's advanced process technologies."

Leading-edge applications moving to chiplet architectures include next-generation 51.2 Terabit per second (Tbps) ASICs for network switches, where 112G XSR links will connect the digital switch ASIC die to CPO engines. In AI/ML and HPC SoCs, the 112G XSR PHY can be used to bridge purpose-built accelerator chiplets for natural language processing, video transcoding and image recognition. Another popular use case is the die disaggregation of large SoCs, hitting reticle size limits for manufacturable yields, into multiple smaller die connected using XSR links over organic substrate. Increasingly, these advanced applications are implemented on TSMC's N7 process.

"This important milestone highlights Rambus' leadership in high-speed SerDes enabling the industry's highest value and most demanding applications," said Hemant Dhulla, vice president and general manager of IP cores at Rambus. "At an industry-leading power efficiency of sub-picojoule per bit, and unidirectional bandwidth approaching two terabit per second per millimeter, we are very proud to offer our 112G XSR/USR solution in partnership with TSMC."

Availability
The Rambus 112G XSR/USR PHY is available today for licensing and integrating into chiplet and SoC designs.

Additional Information
For additional details about the Rambus 112G XSR/USR PHY, please go to https://www.rambus.com/interface-ip/serdes/112g-xsr-phy/

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Company website: rambus.com
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About Rambus Inc.
Rambus is a premier silicon IP and chip provider that makes data faster and safer. With 30 years of innovation, we continue to develop the foundational technology for all modern computing systems. Leveraging our semiconductor expertise, Rambus solutions speed performance, expand capacity and improve security for today's most demanding applications. From data center and edge to artificial intelligence and automotive, our interface and security IP, and memory interface chips enable SoC and system designers to deliver their vision of the future. For more information, visit rambus.com.

Press Contact:
Cori Pasinetti
Rambus Corporate Communications
t: (408) 462-8306
cpasinetti@rambus.com

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SOURCE Rambus Inc.

FAQ

What is Rambus' new product announced in June 2020?

Rambus announced the launch of the 112G XSR/USR PHY on TSMC's 7nm process.

How does the 112G XSR/USR PHY benefit chiplet architectures?

It provides unmatched power and area efficiency for next-generation applications.

What applications are targeted by Rambus' 112G XSR/USR PHY?

It targets data centers, networking, 5G, HPC, and AI/ML applications.

When was the 112G XSR/USR PHY made available for licensing?

The product is available for licensing as of June 17, 2020.

Which semiconductor process is the 112G XSR/USR PHY based on?

It is based on TSMC's industry-leading 7nm process technology.