Cadence Accelerates Hyperscale SoC Design with Next-Generation 112G Extended Long-Reach SerDes IP on TSMC’s N4P Process

Rhea-AI Summary

Cadence Design Systems has launched its new 112G Extended Long-Reach (112G-ELR) SerDes IP on TSMC’s N4P process, aimed at advancing hyperscale ASICs, AI/ML accelerators, and 5G infrastructure. This innovative technology supports an insertion loss of 43dB and a bit error rate of 10^-7, delivering significant performance margins and robust system capabilities for challenging channels. The IP, compliant with IEEE and OIF standards, excels in power, performance, and area efficiency, catering to a variety of reach applications from 1G to 112G. Cadence’s collaboration with TSMC promises to enhance customer design solutions, effectively addressing industry challenges.

The 112G-ELR SerDes PHY is currently available for customer engagements, reinforcing Cadence’s leadership in high-performance connectivity.

Positive

• Launch of 112G-ELR SerDes IP enhances Cadence's offerings in high-speed data transfer.
• Performance margin exceeding standard long-reach specifications boosts competitiveness.
• Collaboration with TSMC enhances technology advancement for customers in hyperscale and AI/ML sectors.
• Support for a wide range of applications (ELR, LR, MR, VSR) broadens market reach.

Negative

• None.

Highlights:

• DSP-based, flexible-rate SerDes IP is optimized for PPA for next-generation cloud networking, AI/ML, and 5G wireless applications
• New architecture delivers exceptional ELR performance and enables system robustness for lossy and reflective channels
• The IP supports ELR, LR, MR and VSR applications and provides a flexible power-saving capability over different channels

SAN JOSE, Calif.--(BUSINESS WIRE)-- Cadence Design Systems, Inc. (Nasdaq: CDNS) today unveiled its 112G Extended Long-Reach (112G-ELR) SerDes IP on TSMC’s N4P process for hyperscale ASICs, artificial intelligence/machine learning (AI/ML) accelerators, switch fabric system-on-chips (SoCs) and 5G wireless infrastructure. The extended long-reach SerDes PHY supports insertion loss (IL) of 43db with BER of 10^e-7—thereby providing additional performance margin beyond the standard long-reach specifications—and enables exceptional system robustness for lossy and reflective channels observed in open box platforms as well as lengthy direct attach copper (DAC) cables.

The Cadence^® 112G-ELR SerDes PHY IP on TSMC’s N4P process, a performance-focused enhancement of the TSMC 5nm technology platform, incorporates industry-leading digital signal processor (DSP)-based SerDes architecture with maximum likelihood sequence detection (MLSD) and reflection cancellation technology. The SerDes PHY IP is compliant with IEEE and OIF Long-Reach (LR) standards while providing extra performance margin for ELR applications. The optimized power, performance and area are ideal for different user scenarios, including high port-density applications. In addition to ELR and LR channels, the IP also supports Medium Reach (MR) and Very Short Reach (VSR) applications with a flexible power-saving capability over different channels. The supported data rates range from 1G to 112G with NRZ and PAM4 signaling, enabling reliable high-speed data transfer over backplane, direct-attached cable (DAC), chip-to-chip and chip-to-module channels.

“Cadence’s latest 112G-ELR IP on TSMC’s N4P process will benefit our mutual customers with significant performance improvement in silicon, helping them address design challenges with the continuous technology advancement from Cadence’s leading IP solutions and TSMC’s advanced process technologies,” said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. “Our latest collaboration with Cadence promotes the development of new technologies for hyperscale, AI/ML, 5G infrastructure and other applications.”

“Our next-generation 112G-ELR SerDes on TSMC N4P solution offers exceptional performance margin and system robustness for customer applications,” said Sanjive Agarwala, corporate vice president and general manager of the IP Group at Cadence. “Our close collaborations with leading hyperscale and data center customers have given us insight into the stringent industry requirements, resulting in enhanced architecture that offers improvements on all key parameters for 112G SerDes. Our 112G-ELR SerDes solution on TSMC’s N4P process further solidifies our leadership position with high-performance connectivity IP offerings for hyperscale data centers, and customers can also enjoy the benefits associated with the TSMC N4P process technology.”

Cadence currently has the 112G-ELR on TSMC N4P test chip silicon in-house, demonstrating optimal performance. The Cadence 112G-ELR SerDes solution on TSMC’s N4P process is available for broad customer engagements now. Cadence has built a large customer base for its PAM4 SerDes by enabling different variations. The 112G-ELR SerDes PHY IP on TSMC’s N4P process is part of the broader Cadence IP portfolio and supports the Cadence Intelligent System Design^™ strategy, which enables advanced-node SoC design excellence. For more information on the 112G-ELR SerDes, please visit www.cadence.com/go/112gelr.

About Cadence

Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For nine years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at www.cadence.com.

© 2023 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

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Source: Cadence Design Systems, Inc.

FAQ

What is Cadence's new product announced in the press release?

Cadence has announced the 112G Extended Long-Reach (112G-ELR) SerDes IP on TSMC’s N4P process.

What applications does the 112G-ELR SerDes IP support?

It supports hyperscale ASICs, AI/ML accelerators, switch fabric SoCs, and 5G wireless infrastructure.

What performance specifications are associated with the 112G-ELR SerDes IP?

The IP supports an insertion loss of 43dB and a bit error rate of 10e-7, providing superior performance.

How does the 112G-ELR SerDes IP aid in design challenges?

It offers significant performance improvement and robust system capabilities for lossy and reflective channels.

Is the 112G-ELR SerDes available for customer engagement?

Yes, the 112G-ELR SerDes PHY IP is currently available for broad customer engagements.