Applied Materials Unveils Chip Wiring Innovations for More Energy-Efficient Computing
Applied Materials has unveiled significant advancements in chip wiring, introducing the industry’s first use of ruthenium in high-volume production to scale copper chip wiring to the 2nm node and beyond.
These innovations include a new enhanced low-k dielectric material, reducing chip capacitance and strengthening chips for 3D stacking.
The new binary metal liner of ruthenium and cobalt reduces the liner thickness by 33% and electrical line resistance by 25%, enhancing chip performance and power consumption.
These technologies are being adopted by major chipmakers like Samsung and TSMC and are expected to expand Applied's market opportunity in wiring, potentially increasing it to $7 billion per 100K wafer starts per month.
- Introduction of ruthenium in high-volume production to enable copper chip wiring to scale to 2nm and beyond.
- New enhanced low-k dielectric material reduces chip capacitance and strengthens chips for 3D stacking.
- Binary metal liner of ruthenium and cobalt reduces liner thickness by 33% and electrical line resistance by 25%.
- Innovations are being adopted by leading chipmakers like Samsung and TSMC.
- Market opportunity in wiring could increase to $7 billion per 100K wafer starts per month.
- None.
Applied Materials' unveiling of innovations for chip wiring using ruthenium and enhanced low-k dielectric materials marks a significant leap in semiconductor engineering. The implementation of ruthenium in high-volume production is groundbreaking, as it enables scaling copper wiring to the 2nm node and beyond, while significantly reducing electrical resistance by
The enhanced low-k dielectric material, which reduces chip capacitance and strengthens chips for 3D stacking, addresses a key challenge in Moore's Law scaling: the mechanical weakness of chips as they scale down. This innovation not only supports further miniaturization but also improves the integrity of chips during high-stress processes like 3D stacking.
The integrated materials solution, combining technologies in a high-vacuum system to scale copper wiring, demonstrates Applied Materials' strong leadership in the semiconductor manufacturing space. The adoption of these technologies by leading logic and DRAM chipmakers underscores their critical importance to the industry.
For retail investors, these innovations suggest that Applied Materials is proactively addressing the most pressing technical challenges in chip manufacturing, potentially leading to sustained demand and market leadership in the semiconductor sector.
The introduction of these new technologies by Applied Materials is likely to have a positive impact on its financial performance. The company's ability to scale chip wiring to the 2nm node and beyond by using ruthenium and enhanced low-k dielectric materials could lead to a robust increase in orders from semiconductor manufacturers. This is particularly relevant given the increasing demand for energy-efficient and high-performance chips in the AI and computing industries.
Applied Materials' dominance in the chip wiring process technologies market is evident from its expanding served available market opportunity, which has increased from $1 billion to $6 billion per 100,000 wafer starts per month at the 3nm node. With the introduction of backside power delivery, this opportunity could further expand by $1 billion, highlighting a strong growth trajectory for the company.
Retail investors should note that the adoption of these innovations by major industry players like Samsung and TSMC provides a strong validation of their effectiveness and market applicability. This widespread acceptance is likely to drive revenue growth and enhance Applied Materials' market share in the semiconductor equipment industry.
- Industry’s first use of ruthenium in high-volume production enables copper chip wiring to be scaled to the 2nm node and beyond and reduces resistance by as much as
25% - New enhanced low-k dielectric material reduces chip capacitance and strengthens logic and DRAM chips for 3D stacking
SANTA CLARA, Calif., July 08, 2024 (GLOBE NEWSWIRE) -- Applied Materials, Inc. today introduced materials engineering innovations designed to increase the performance-per-watt of computer systems by enabling copper wiring to scale to the 2nm logic node and beyond.
“The AI era needs more energy-efficient computing, and chip wiring and stacking are critical to performance and power consumption,” said Dr. Prabu Raja, President of the Semiconductor Products Group at Applied Materials. “Applied’s newest integrated materials solution enables the industry to scale low-resistance copper wiring to the emerging angstrom nodes, while our latest low-k dielectric material simultaneously reduces capacitance and strengthens chips to take 3D stacking to new heights.”
Overcoming the Physics Challenges of Classic Moore’s Law Scaling
Today’s most advanced logic chips can contain tens of billions of transistors connected by more than 60 miles of microscopic copper wiring. Each layer of a chip’s wiring begins with a thin film of dielectric material, which is etched to create channels that are filled with copper. Low-k dielectrics and copper have been the industry’s workhorse wiring combination for decades, allowing chipmakers to deliver improvements in scaling, performance and power-efficiency with each generation.
However, as the industry scales to 2nm and below, thinner dielectric material renders chips mechanically weaker, and narrowing the copper wires creates steep increases in electrical resistance that can reduce chip performance and increase power consumption.
Enhanced Low-k Dielectric Reduces Interconnect Resistance and Strengthens Chips for 3D Stacking
Applied’s Black Diamond™ material has led the industry for decades, surrounding copper wires with a low-dielectric-constant – or “k-value” – film engineered to reduce the buildup of electrical charges that increase power consumption and cause interference between electrical signals.
Applied today introduced an enhanced version of Black Diamond, the latest in the company’s Producer™ Black Diamond™ PECVD* family. This new material reduces the minimum k-value to enable scaling to 2nm and below, while offering increased mechanical strength which is becoming critical as chipmakers and systems companies take 3D logic and memory stacking to new heights.
The latest Black Diamond technology is being adopted by all leading logic and DRAM chipmakers.
New Binary Metal Liner Enables Ultrathin Copper Wires
To scale chip wiring, chipmakers etch each layer of low-k film to create trenches, then deposit a barrier layer that prevents copper from migrating into the chip and creating yield issues. The barrier is then coated with a liner that ensures adhesion during the final copper reflow deposition sequence, which slowly fills the remaining volume with copper.
As chipmakers further scale the wiring, the barrier and liner take up a larger percentage of the volume intended for wiring, and it becomes physically impossible to create low-resistance, void-free copper wiring in the remaining space.
Today, Applied Materials publicly introduced its latest IMS™ (Integrated Materials Solution™) which combines six different technologies in one high-vacuum system, including an industry-first combination of materials that enables chipmakers to scale copper wiring to the 2nm node and beyond. The solution is a binary metal combination of ruthenium and cobalt (RuCo), which simultaneously reduces the thickness of the liner by 33 percent to 2nm, produces better surface properties for void-free copper reflow, and reduces electrical line resistance by up to 25 percent to improve chip performance and power consumption.
The new Applied Endura™ Copper Barrier Seed IMS™ with Volta™ Ruthenium CVD* is being adopted by all leading logic chipmakers and began shipping to customers at the 3nm node. An animation of the technology can be viewed here.
Customer Comments
“While advances in patterning are driving continued device scaling, critical challenges remain in other areas including interconnect wiring resistance, capacitance and reliability,” said Sunjung Kim, VP & Head of Foundry Development Team at Samsung Electronics. “To help overcome these challenges, Samsung is adopting multiple materials engineering innovations that extend the benefits of scaling to the most advanced nodes.”
“The semiconductor industry must deliver dramatic improvements in energy-efficient performance to enable sustainable growth in AI computing,” said Dr. Y.J. Mii, Executive Vice President and Co-Chief Operating Officer at TSMC. “New materials that reduce interconnect resistance will play an important role in the semiconductor industry, alongside other innovations to improve overall system performance and power.”
A Growing Wiring Opportunity
Applied is the industry leader in chip wiring process technologies. From the 7nm node to the 3nm node, interconnect wiring steps have approximately tripled, increasing Applied’s served available market opportunity in wiring by more than
The new chip wiring products, along with other materials engineering innovations for making future AI chips, will be discussed at Applied’s SEMICON West 2024 Technology Breakfast. The presentation and other materials from the event will be available on the Applied Materials website at: https://ir.appliedmaterials.com on Tuesday, July 9, 2024 at approximately 9:00 a.m. ET / 6:00 a.m. PT.
*PECVD = Plasma-Enhanced Chemical Vapor Deposition
*CVD = Chemical Vapor Deposition
Forward-Looking Statements
This press release contains forward-looking statements, including those regarding anticipated benefits of our new products and technologies, expected growth and trends in our businesses and markets, industry outlooks and demand drivers, technology transitions, and other statements that are not historical facts. These statements and their underlying assumptions are subject to risks and uncertainties and are not guarantees of future performance. Factors that could cause actual results to differ materially from those expressed or implied by such statements include, without limitation: failure to realize anticipated benefits of our new products and technologies; the level of demand for semiconductors and for our products and technologies; customers’ technology and capacity requirements; the introduction of new and innovative technologies, and the timing of technology transitions; market acceptance of existing and newly developed products; the ability to obtain and protect intellectual property rights in technologies; our ability to ensure compliance with applicable law, rules and regulations; and other risks and uncertainties described in our SEC filings, including our recent Forms 10-Q and 8-K. All forward-looking statements are based on management’s current estimates, projections and assumptions, and we assume no obligation to update them.
About Applied Materials
Applied Materials, Inc. (Nasdaq: AMAT) is the leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. Our expertise in modifying materials at atomic levels and on an industrial scale enables customers to transform possibilities into reality. At Applied Materials, our innovations make possible a better future. Learn more at www.appliedmaterials.com.
Applied Materials Contact:
Ricky Gradwohl (editorial/media) 408.235.4676
Michael Sullivan (financial community) 408.986.7977
Photos accompanying this announcement are available at
https://www.globenewswire.com/NewsRoom/AttachmentNg/96098774-3afd-4e4a-9f5c-e0ba8d523bc2
https://www.globenewswire.com/NewsRoom/AttachmentNg/fd0d0edb-65ea-49ab-a66b-1f5bc5265b16
https://www.globenewswire.com/NewsRoom/AttachmentNg/8c6a061b-92da-4b37-a475-8f57e3884ef4
FAQ
What are the new chip wiring innovations introduced by Applied Materials?
How does the new binary metal liner benefit chip performance?
Which chipmakers are adopting Applied Materials' new technologies?
How will Applied Materials' innovations impact its market opportunity?
When was the press release on Applied Materials' chip wiring innovations published?
