Synopsys and TSMC Pave the Path for Trillion-Transistor AI and Multi-Die Chip Design
Synopsys and TSMC announced their collaboration to enhance EDA and IP solutions for AI and multi-die chip designs on TSMC's advanced N2 and A16 processes. Key advancements include:
- Production-ready AI-driven EDA flows, powered by Synopsys.ai, delivering enhanced results and accelerating design node migration.
- New backside power delivery capabilities on TSMC's A16 for efficient power distribution and system performance.
- Joint efforts with Ansys to address thermal and power integrity challenges using CoWoS interposer packaging.
- Development of 40G UCIe, HBM4, and 3DIO IP on advanced TSMC nodes to optimize latency, power, performance, and area.
Synopsys' AI-driven EDA suite and silicon-proven IP have significantly improved productivity and performance for advanced AI chip designs. The collaboration has also enabled cloud-ready EDA tools for mutual customers, enhancing the design process for multi-die architectures.
Synopsys e TSMC hanno annunciato la loro collaborazione per migliorare le soluzioni EDA e IP per l'IA e i progettazioni di chip multi-die sui processi avanzati N2 e A16 di TSMC. I principali progressi includono:
- Flussi EDA pronti per la produzione, guidati da Synopsys.ai, che offrono risultati migliorati e accelerano la migrazione del nodo di progettazione.
- Nuove capacità di distribuzione dell'alimentazione sul retro dell'A16 di TSMC per una distribuzione efficiente dell'energia e delle prestazioni del sistema.
- Sforzi congiunti con Ansys per affrontare le sfide relative all'integrità termica e della potenza utilizzando il confezionamento CoWoS interposer.
- Sviluppo di 40G UCIe, HBM4 e IP 3DIO su nodi avanzati TSMC per ottimizzare latenza, potenza, prestazioni e area.
La suite EDA guidata dall'IA e l'IP collaudato di Synopsys hanno notevolmente migliorato la produttività e le prestazioni per i progetti avanzati di chip IA. La collaborazione ha anche abilitato strumenti EDA pronti per il cloud per i clienti comuni, migliorando il processo di progettazione per le architetture multi-die.
Synopsys y TSMC anunciaron su colaboración para mejorar las soluciones EDA e IP para IA y diseño de chips de múltiples die en los procesos avanzados N2 y A16 de TSMC. Los principales avances incluyen:
- Flujos de EDA listos para producción, impulsados por Synopsys.ai, que ofrecen resultados mejorados y aceleran la migración del nodo de diseño.
- Nuevas capacidades de entrega de energía posterior en el A16 de TSMC para una distribución eficiente de energía y rendimiento del sistema.
- Esfuerzos conjuntos con Ansys para abordar los desafíos de integridad térmica y de energía utilizando empaques interposer CoWoS.
- Desarrollo de 40G UCIe, HBM4 y IP 3DIO en nodos avanzados de TSMC para optimizar latencia, potencia, rendimiento y área.
El paquete EDA impulsado por IA y el IP comprobado de Synopsys han mejorado significativamente la productividad y el rendimiento para diseños avanzados de chips de IA. La colaboración también ha habilitado herramientas de EDA listas para la nube para clientes mutuos, mejorando el proceso de diseño para arquitecturas de múltiples die.
Synopsys와 TSMC는 TSMC의 고급 N2 및 A16 공정에서 AI 및 멀티 다이 칩 설계를 위한 EDA 및 IP 솔루션을 향상시키기 위한 협력을 발표했습니다. 주요 개발 사항은 다음과 같습니다:
- Synopsys.ai가 지원하는 생산 준비 완료 AI 기반 EDA 흐름으로, 향상된 결과를 제공하고 설계 노드 이전을 가속화합니다.
- 효율적인 전력 분배와 시스템 성능을 위한 TSMC의 A16에 새로운 역면 전력 전달 기능이 추가되었습니다.
- CoWoS 인터포저 포장을 사용하여 열 및 전력 무결성 문제를 다루기 위해 Ansys와 공동으로 노력하고 있습니다.
- 지연 시간, 전력, 성능 및 면적 최적화를 위해 고급 TSMC 노드에서 40G UCIe, HBM4 및 3DIO IP를 개발하고 있습니다.
Synopsys의 AI 기반 EDA 제품군과 검증된 IP는 고급 AI 칩 설계를 위해 생산성과 성능을 크게 향상시켰습니다. 이번 협력은 공동 고객을 위한 클라우드 준비 완료 EDA 도구도 가능하게 하여 멀티 다이 아키텍처의 설계 프로세스를 개선했습니다.
Synopsys et TSMC ont annoncé leur collaboration pour améliorer les solutions EDA et IP pour l'IA et les conceptions de puces multi-die sur les processus avancés N2 et A16 de TSMC. Les avancées clés comprennent :
- Flux EDA prêts pour la production, propulsés par Synopsys.ai, offrant des résultats améliorés et accélérant la migration des nœuds de conception.
- Nouvelles capacités de distribution d'alimentation par l'arrière sur l'A16 de TSMC pour une distribution efficace de l'énergie et des performances système.
- Efforts conjoints avec Ansys pour relever les défis d'intégrité thermique et de puissance grâce à l'emballage CoWoS interposer.
- Développement de 40G UCIe, HBM4 et 3DIO IP sur les nœuds avancés de TSMC pour optimiser la latence, la puissance, les performances et la surface.
La suite EDA alimentée par l'IA et l'IP éprouvée de Synopsys ont significativement amélioré la productivité et les performances pour les conceptions avancées de puces IA. La collaboration a également permis de disposer d'outils EDA prêts pour le cloud pour les clients communs, améliorant le processus de conception des architectures multi-die.
Synopsys und TSMC haben ihre Zusammenarbeit angekündigt, um die EDA- und IP-Lösungen für KI- und Multi-DIE-Chip-Designs auf TSMCs fortschrittlichen N2- und A16-Prozessen zu verbessern. Zu den wichtigsten Fortschritten gehören:
- Produktionsbereite, KI-gestützte EDA-Flows, angetrieben von Synopsys.ai, die verbesserte Ergebnisse liefern und die Migration zwischen Designknoten beschleunigen.
- Neue Rückseitenleistungstransferfähigkeit auf TSMCs A16 für eine effiziente Energieverteilung und Systemleistung.
- Gemeinsame Anstrengungen mit Ansys zur Bewältigung von thermischen und leistungsbezogenen Herausforderungen mithilfe von CoWoS-Interposer-Verpackungen.
- Entwicklung von 40G UCIe, HBM4 und 3DIO IP auf fortschrittlichen TSMC-Knoten zur Optimierung von Latenz, Leistung, Effizienz und Fläche.
Die KI-gesteuerte EDA-Suite und die siliconbasierten IPs von Synopsys haben die Produktivität und Leistung bei fortschrittlichen KI-Chip-Designs erheblich verbessert. Die Zusammenarbeit hat auch cloudfähige EDA-Tools für gemeinsame Kunden ermöglicht, was den Designprozess für Multi-DIE-Architekturen verbessert.
- Collaboration with TSMC delivers advanced EDA and IP solutions on N2 and A16 processes.
- AI-driven EDA flows enhance productivity and accelerate design node migration.
- New backside power delivery capabilities on A16 improve power distribution and system performance.
- Joint efforts with Ansys address thermal and power integrity challenges using CoWoS interposer packaging.
- Development of 40G UCIe, HBM4, and 3DIO IP optimizes latency, power, performance, and area.
- Cloud-ready EDA tools enhance the design process for multi-die architectures.
- None.
Insights
This collaboration between Synopsys and TSMC is highly significant for the semiconductor industry, especially in the realm of advanced AI chip design. The partnership focuses on optimizing EDA tools and IP for TSMC's cutting-edge N2 and A16 processes, which is important for pushing the boundaries of chip performance and efficiency.
Key highlights include:
- AI-driven EDA flows for TSMC's N2 process, enhancing design quality and accelerating node migration
- Development of backside power delivery capabilities for A16, improving power distribution and system performance
- Multi-physics flow for CoWoS interposer packaging, addressing thermal and power integrity challenges
- New 40G UCIe, HBM4 and 3DIO IP optimizations for advanced nodes
This collaboration is particularly important as it enables the design of trillion-transistor AI chips and advanced multi-die architectures. The focus on AI-driven tools and 3D packaging solutions indicates a clear direction towards more complex, high-performance computing systems necessary for future AI applications.
For Synopsys investors, this partnership reinforces the company's position as a leader in EDA and semiconductor IP, potentially driving future revenue growth as demand for advanced AI chips increases.
The Synopsys-TSMC collaboration represents a significant leap forward in enabling the next generation of AI hardware. The focus on trillion-transistor designs and multi-die architectures is important for meeting the exponential growth in computational demands of AI applications.
Key technological advancements include:
- Synopsys.ai-powered EDA flows optimized for TSMC's N2 process, which will likely result in more efficient and powerful AI chips
- 3DSO.ai for AI-driven system analysis in 3D chip designs, critical for optimizing complex multi-die systems
- Advanced IP developments like 40G UCIe and HBM4, essential for high-bandwidth, low-latency communication in AI systems
These innovations address critical challenges in AI chip design, such as power efficiency, thermal management and system integration. The collaboration's emphasis on 2.5D/3D architectures and advanced packaging technologies like CoWoS is particularly important, as it enables the creation of more sophisticated AI systems that can overcome the limitations of traditional 2D chip designs.
For the AI industry, this partnership promises to accelerate the development of more powerful and efficient hardware, potentially enabling new AI applications and improving the performance of existing ones across various sectors.
Optimized EDA and IP Solutions Deliver Enhanced Compute Performance, Power and Engineering Productivity for TSMC N2 and A16 Processes
Highlights
- Production-ready AI-driven EDA flows, powered by Synopsys.ai, on N2 deliver exceptional quality of results and accelerate design node migration for industry leaders
- Developing new backside power delivery capabilities on TSMC's A16 to enable efficient power distribution and system performance
- Joint TSMC, Synopsys and Ansys multi-physics flow supporting CoWoS interposer packaging addresses thermal and power integrity challenges
- Synopsys 3DSO.ai delivers AI-driven system analysis for maximum quality of results with support for TSMC's 3DFabric
- New development of 40G UCIe, HBM4 and 3DIO IP on advanced TSMC nodes optimizes latency, power, performance and area
"TSMC is excited to collaborate with Synopsys to develop pioneering EDA and IP solutions tailored for the rigorous compute demands of AI designs on TSMC advanced process and 3DFabric technologies," said Dan Kochpatcharin, head of the Ecosystem and Alliance Management Division at TSMC. "The results of our latest collaboration across Synopsys' AI-driven EDA suite and silicon-proven IP have helped our mutual customers significantly enhance their productivity and deliver remarkable performance, power, and area results for advanced AI chip designs.
"For decades, Synopsys has closely collaborated with TSMC, providing mission-critical EDA and IP solutions spanning all generations of TSMC's most advanced nodes," said Sanjay Bali, senior vice president of EDA product management at Synopsys. "This partnership has been instrumental in helping our mutual customers accelerate their innovation in the AI era and advance the future of semiconductor designs. Together, we are pushing the boundaries of what's possible, enabling groundbreaking advancements in performance, power efficiency, and engineering productivity."
Synopsys AI-Driven EDA Design Flows Boost PPA and Engineering Productivity
Industry leaders have embraced Synopsys AI-driven EDA flows, powered by Synopsys.ai for their advanced chip designs on N2.
"Synopsys' certified Custom Compiler and PrimeSim solutions provide the performance and productivity gains that enable our designers to meet the silicon demands of high-performance analog design on the TSMC N2 process," said Ching San Wu, Corporate VP at MediaTek. "Expanding our collaboration with Synopsys makes it possible for us to leverage the full potential of their AI-driven flow to accelerate our design migration and optimization efforts, improving the process required for delivering our industry-leading SoCs to multiple verticals."
In addition, Synopsys is collaborating with TSMC on the new backside routing capabilities supporting TSMC's A16 process in the Synopsys digital design flow to address power distribution and signal routing for design performance efficiency and density optimization. Interoperable process design kits (iPDKs) and Synopsys IC Validator™ physical verification runsets are available for design teams to handle the increasing complexity of physical verification rules and efficiently transition designs to TSMC N2 technology.
To further accelerate chip design, Synopsys and TSMC have enabled Synopsys EDA tools on the cloud through TSMC's Cloud Certification, providing mutual customers with cloud-ready EDA tools that deliver accurate quality of results and seamlessly integrate with TSMC's advanced process technology. Synopsys' cloud-certified tools include synthesis, place and route, static timing and power analysis, transistor-level static timing analysis, custom implementation, circuit simulation, EMIR analysis and design rule checking.
Advancing Multi-Die Innovation with Comprehensive EDA Solutions
Synopsys, Ansys and TSMC have collaborated to address the complex multi-physics challenge for multi-die designs with a comprehensive system analysis flow by leveraging their prime solutions. The most recent flow based on Synopsys 3DIC Compiler unified exploration-to-signoff platform, which integrates 3DSO.ai, combined with Ansys RedHawk-SC™ power integrity signoff platform for digital and 3D integrated circuits, enhances the thermal and IR-aware timing analysis. Synopsys 3DIC Compiler is a TSMC-certified platform supporting 3Dblox, TSMC's 3DFabric, which includes TSMC-SoIC® (System on Integrated Chips) and CoWoS packaging technologies.
"Our collaboration with Synopsys and TSMC exemplifies our collective commitment to driving innovation and enabling the future of AI and multi-die chip design," said John Lee, vice president and general manager, semiconductor, electronics and optics business at Ansys. "Together, we are tackling the multi-physics challenges inherent in multi-die architectures, helping our mutual customers achieve golden signoff accuracy for chip, package, and system-level effects within the Synopsys design environment on the latest TSMC technologies."
Reduce Risk with Silicon-Proven IP
Synopsys' comprehensive multi-die test solutions, available with the Synopsys UCIe and HBM3 IP, ensure multi-die package health during manufacturing test and in-field. In collaboration with TSMC, Synopsys has taped out a test chip utilizing TSMC's CoWoS interposer technology with full support for test, monitor, debug, and repair capabilities. The diagnosis, traceability, and mission mode signal integrity monitoring allow in-design, in-ramp, in-production, and in-field optimization for purposes such as predictive maintenance. The Monitoring, Test, and Repair (MTR) IP for UCIe PHY provides testability at the die, die-to-die interface and multi-die package levels.
Synopsys has achieved multiple silicon successes for UCIe and HBM3 IP solutions across N3E and N5 process technologies, accelerating IP integration and minimizing risk. Latest developments of the Synopsys UCIe IP, operating up to 40G, allows maximum bandwidth and energy efficiency without the need for additional area while the HBM4 and 3DIO IP solutions accelerate heterogeneous integration of 3D stacked-dies on TSMC's advanced processes.
Additional Resources
- LinkedIn article: Synopsys-TSMC Successful Tapeout of a Test Chip Featuring a Multi-Die Design Using TSMC's CoWoS Technology
- Synopsys is hosting several demonstrations at the TSMC OIP Ecosystem Forum today in
Santa Clara at Booth #204
About Synopsys
Catalyzing the era of pervasive intelligence, Synopsys, Inc. (Nasdaq: SNPS) delivers trusted and comprehensive silicon to systems design solutions, from electronic design automation to silicon IP and system verification and validation. We partner closely with semiconductor and systems customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. Learn more at www.synopsys.com.
Editorial Contact
Kelli Wheeler
Synopsys, Inc.
(650) 584-5000
corp-pr@synopsys.com
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SOURCE Synopsys, Inc.
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