Cadence Design Systems - CDNS STOCK NEWS

Cadence Design Systems reported a revenue of $1.022 billion for Q1 2023, up from $902 million in Q1 2022. The company achieved a GAAP operating margin of 32% and a net income of $242 million ($0.89 per diluted share), compared to a 35% operating margin and $235 million ($0.85 per diluted share) in the prior year. Non-GAAP results showed an operating margin of 42% and net income of $351 million ($1.29 per diluted share). The outlook for 2023 revenue growth is now approximately 14%, with expected total revenue between $4.03 billion to $4.07 billion.

For Q2 2023, revenue is anticipated to fall between $960 million to $980 million, and GAAP net income is projected at $0.73 to $0.77 per diluted share.

Cadence Design Systems (CDNS) announced the successful tapeout of its 16G UCIe 2.5D advanced package IP on TSMC's 3nm N3E process technology. This innovation supports ultra-high bandwidth density and low-power performance, crucial for AI, mobile, and automotive applications. The UCIe IP facilitates chiplet integration, addressing the industry's shift away from traditional monolithic designs. Cadence has engaged with Tier 1 customers, showcasing the solution's capabilities to streamline integration processes. Key components include the UCIe Advanced Package PHY for high bandwidth, the cost-efficient UCIe Standard-Package PHY, and a versatile UCIe Controller. The milestone reflects Cadence's commitment to interoperability and innovation within the chiplet ecosystem.

Cadence Design Systems has launched its new 112G Extended Long-Reach (112G-ELR) SerDes IP on TSMC’s N4P process, aimed at advancing hyperscale ASICs, AI/ML accelerators, and 5G infrastructure. This innovative technology supports an insertion loss of 43dB and a bit error rate of 10^-7, delivering significant performance margins and robust system capabilities for challenging channels. The IP, compliant with IEEE and OIF standards, excels in power, performance, and area efficiency, catering to a variety of reach applications from 1G to 112G. Cadence’s collaboration with TSMC promises to enhance customer design solutions, effectively addressing industry challenges.

The 112G-ELR SerDes PHY is currently available for customer engagements, reinforcing Cadence’s leadership in high-performance connectivity.

Cadence Design Systems has launched the new Cadence Virtuoso Studio, a next-generation custom design platform that significantly enhances design productivity by over 3X. This platform integrates seamlessly with existing Cadence technologies, facilitating complex semiconductor and 3D-IC designs. Leveraging 30 years of industry experience, Virtuoso Studio addresses challenges in managing larger designs, enabling quicker time-to-market for customers.

Features include advanced automation for layout placement, cloud-readiness for scalable solutions, and generative AI tools that streamline design migration. The platform supports heterogeneous integration for next-gen applications, ensuring design accuracy and efficiency through innovative tools and optimization techniques.

Cadence Design Systems has announced the recipients of its Women in Technology Scholarship, honoring accomplished women pursuing technical degrees. The awardees were selected based on their strong academic performance, community engagement, leadership qualities, and endorsements from educators. The scholarship aims to support these women as they strive to innovate in the technology sector. A video featuring interviews with the scholarship recipients details their personal experiences and future aspirations in technology. Cadence is committed to fostering diversity and encouraging future leaders in tech.

Cadence Design Systems, Inc. (CDNS) has announced successful interoperability of its LPDDR5X memory interface IP with SK hynix’s LPDDR5T mobile DRAM, achieving speeds above the LPDDR5X standard. The LPDDR5X IP design operates at 8533Mbps, while the LPDDR5T technology reaches 9600Mbps. This high-performance memory solution is designed with a scalable architecture and is positioned for future memory developments, enhancing its adaptability. The technology is now available for customer engagements, supporting Cadence’s Intelligent System Design strategy, which focuses on optimized SoC design. These advancements open new opportunities in sectors such as AI and augmented reality, marking a significant milestone for Cadence in the memory interface space.

Cadence Design Systems (CDNS) has announced an expanded collaboration with TSMC and Microsoft to enhance physical verification for giga-scale digital designs on the Microsoft Azure cloud. This collaboration allows customers to utilize the Cadence Pegasus Verification System along with TSMC technology, directly benefiting from the Cadence CloudBurst Platform.

Initial outcomes show that using the Pegasus system in the cloud can improve performance and reduce compute costs by over 20%. The system's FlexCompute technology dynamically manages CPU resources, thus optimizing utilization and reducing turnaround times. The partnership aims to help design teams effectively manage large designs while meeting tight deadlines and budget constraints.