Cadence Tapes Out 16G UCIe Advanced Package IP on TSMC’s N3E Process Technology

Rhea-AI Summary

Cadence Design Systems (CDNS) announced the successful tapeout of its 16G UCIe 2.5D advanced package IP on TSMC's 3nm N3E process technology. This innovation supports ultra-high bandwidth density and low-power performance, crucial for AI, mobile, and automotive applications. The UCIe IP facilitates chiplet integration, addressing the industry's shift away from traditional monolithic designs. Cadence has engaged with Tier 1 customers, showcasing the solution's capabilities to streamline integration processes. Key components include the UCIe Advanced Package PHY for high bandwidth, the cost-efficient UCIe Standard-Package PHY, and a versatile UCIe Controller. The milestone reflects Cadence's commitment to interoperability and innovation within the chiplet ecosystem.

Positive

• Successful tapeout of the 16G UCIe 2.5D advanced package IP on TSMC's 3nm process.
• Engagement with Tier 1 customers indicates strong market demand.
• The UCIe IP enhances chiplet integration, crucial for high-performance applications.

Negative

• None.

Complete high-performance 2.5D package solution enables heterogeneous integration

SAN JOSE, Calif.--(BUSINESS WIRE)-- Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the tapeout of Cadence^® 16G UCIe™ 2.5D advanced package IP on TSMC’s 3nm (N3E) process technology. Implemented on TSMC’s 3DFabric™ CoWoS-S silicon interposer technology, the IP offers ultra-high bandwidth density, efficient low-power performance and superior low latency, making it ideal for applications requiring extreme compute power. Cadence UCIe IP provides an open standard for chiplet die-to-die communication, which is becoming more critical as artificial intelligence/machine learning (AI/ML), mobile, automotive, storage and networking applications are driving the need to move from monolithic integration to system-in-package (SiP) chiplets.

Cadence is currently engaged with a pipeline of Tier 1 customers, and UCIe advanced package IP collateral from the N3E test chip tapeout is shipping and available. The pre-verified solution can save customers time and effort through rapid integration.

The heterogeneous integration of Cadence’s UCIe PHY and controller eases chiplet solutions with die reusability. The complete solution includes the following, which can be delivered with a complement of Cadence Verification IP (VIP) and TLM models:

• UCIe Advanced Package PHY: Designed for a bump pitch that enables greater than 5Tbps/mm of die edge bandwidth density, the UCIe advanced package PHY offers options that allow greater throughput performance while significantly improving power efficiency. It is flexible for integration on multiple types of 2.5D advanced packages, such as silicon interposer, silicon bridge, RDL and fanout-based packaging.
• UCIe Standard-Package PHY: Options allow customers to reduce costs while maintaining high bandwidth and power efficiency. Cadence’s circuit design allows customers to design down to the lower limits of the standard’s bump pitch range to allow maximum BW/mm while also enabling longer reach.
• UCIe Controller: A soft IP that can be synthesized for multiple technology nodes, the UCIe controller is offered in a variety of options for different target applications and enables streaming, PCI Express^® (PCIe^®), and CXL protocols.

“The UCIe Consortium supports companies designing chiplets for use in standard and advanced packaging. We are thrilled to extend our congratulations to Cadence on reaching the tape out milestone for the advanced package test chip which uses the die-to-die interconnect based on the UCIe 1.0 specification,” said Dr. Debendra Das Sharma, chairman at the UCIe Consortium. “Member company advancements in IP (scaling) and VIP (testing) are important components in the ecosystem. When paired with participation in UCIe work groups the industry will continue to see new chiplet based designs entering the market that are based on open industry standards that foster interoperability, compatibility, and innovation.”

“Cadence has been an industry pioneer in chiplet system solution offerings and continues to push the envelope of performance and power efficiency for a wide range of multi-chiplet applications in advanced nodes and packaging architectures,” said Sanjive Agarwala, corporate vice president and general manager of the IP Group at Cadence. “We see great value in aligning interconnect standards across the industry, and UCIe IP serves as a bridge, enabling open chiplet solutions for large SoCs reaching or exceeding the maximum reticle limit for manufacturing. The recent UCIe advanced package tapeout on the TSMC N3E process is a key milestone and commitment toward enabling customers with an open chiplet connectivity standard.”

The Cadence 16G UCIe™ 2.5D advanced package IP supports Cadence’s Intelligent System Design™ strategy, which enables SoC design excellence. For more information, please visit: www.cadence.com/go/ucie16g.

About Cadence

Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For nine years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at www.cadence.com.

© 2023 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. UCIe Consortium, Universal Chiplet Interconnect Express, and UCIe are trademarks of the UCIe Consortium. PCI Express and PCIe are registered trademarks or trademarks of PCI-SIG. SystemC is a trademark of Accellera Systems Initiative Inc. All other trademarks are the property of their respective owners.

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FAQ

What is Cadence's latest announcement regarding the 16G UCIe 2.5D package IP?

Cadence announced the successful tapeout of its 16G UCIe 2.5D advanced package IP on TSMC's 3nm process, focusing on high bandwidth and low power.

How does the UCIe IP enhance chiplet integration for Cadence?

The UCIe IP supports chiplet die-to-die communication, facilitating a shift from monolithic integration to system-in-package designs.

What applications benefit from Cadence's 16G UCIe IP?

The 16G UCIe IP is ideal for applications requiring extreme compute power, including AI, mobile, automotive, and networking.

Who are Cadence's target customers for the new UCIe packaging solutions?

Cadence is currently engaged with a pipeline of Tier 1 customers for their UCIe advanced package IP.

What technologies does the UCIe Controller support?

The UCIe Controller supports streaming, PCI Express, and CXL protocols, making it versatile for various applications.