Cadence Library Characterization Solution Accelerates Delivery and Enhances Quality of Arm Memory Products

Rhea-AI Summary

Cadence Design Systems (NASDAQ: CDNS) announced that Arm is utilizing its Liberate MX Trio Characterization to enhance the quality of embedded memory and speed up market delivery. This solution enabled Arm to reduce memory LVF characterization validation runtime by 7X compared to traditional Monte Carlo simulations. The automated and less error-prone process improved accuracy while minimizing manual efforts and validation time. The adoption of this characterization tool signifies Arm's commitment to meeting evolving memory characterization demands.

Positive

• Arm reduced memory LVF characterization runtime by 7X, enhancing efficiency.
• Liberate MX Trio Characterization improved accuracy and capacity for advanced-node memory designs.

Negative

• None.

Highlights:

• Cadence Liberate MX Trio Characterization enabled Arm to reduce memory LVF characterization validation runtime by 7X
• Arm achieved the accuracy and capacity required to address advanced-node memory characterization challenges

SAN JOSE, Calif.--(BUSINESS WIRE)-- Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that Arm is leveraging Cadence^® Liberate^™ MX Trio Characterization to enhance the quality of its embedded memory instances and compilers and speed time to market. With Liberate MX Trio Characterization, Arm achieved its accuracy and capacity requirements and reduced memory liberty variation format (LVF) characterization validation runtime by 7X when compared with brute-force Monte Carlo simulation.

Liberate MX Trio Characterization, a library characterization solution that is suited for large, advanced-node memory designs, enabled the Arm engineering team to efficiently and accurately perform characterization validation of its embedded memory instances and compilers. Unlike traditional solutions that require tradeoffs between runtime and accuracy, Liberate MX Trio Characterization provided Arm with automated and simulation-based dynamic partitioning to reduce runtime, increase capacity and maintain SPICE-level accuracy. In addition, the Liberate MX Trio Characterization’s probing capabilities helped Arm identify the most critical timing arcs and reduce the manual effort associated with characterization path selection. Simulations on the full RC netlist covering a complete vector set let Arm identify accurate worst-case paths and maintain SPICE-level accuracy. Moving from Arm’s previous brute-force Monte Carlo simulation methodology to the Liberate MX Trio Characterization variation LVF analysis methodology saved Arm weeks of validation time through the solution’s automated and less error-prone methodology.

“Arm has been leveraging the Liberate Trio Characterization Suite for standard cell characterization, so it was an easy choice for us to broaden our deployment with Liberate MX Trio Characterization to address our evolving LVF memory characterization needs,” said Philippe Moyer, VP Design Enablement, Physical Design Group, Arm. “By incorporating Liberate MX Trio Characterization into our methodology, we are improving accuracy, capacity and meeting time-to-market goals with the delivery of our embedded memory instances and compilers.”

“Memory characterization can have a significant impact on signoff accuracy, and Arm was looking for a reliable solution for its embedded memory IP that would help them achieve their accuracy requirements while speeding time to market,” said Sharad Mehrotra, VP of R&D, in the Digital & Signoff Group at Cadence. “Arm joined a community of successful, production-proven Liberate MX Trio Characterization customers, trusting the solution for its memory characterization needs and expanding upon its use of the broader Liberate product portfolio for standard cell power and performance characterization.”

The Liberate MX Trio Characterization is part of the broader digital full flow, which supports the company’s Intelligent System Design^™ strategy and enables SoC design excellence. For more information on Liberate MX Trio Characterization, please visit www.cadence.com/go/liberatemxcs.

About Cadence

Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For eight years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.

© 2022 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All other trademarks are the property of their respective owners.

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FAQ

What is the significance of Cadence's Liberate MX Trio Characterization for Arm's memory validation?

The Liberate MX Trio Characterization significantly reduces Arm's memory LVF characterization validation runtime by 7X and improves accuracy.

How does Cadence's solution impact Arm's time to market?

By utilizing Cadence's solution, Arm enhances efficiency, speeding up the delivery of its embedded memory instances and compilers.

What are the main advantages of the Liberate MX Trio Characterization for advanced-node memory designs?

The solution offers automated, simulation-based dynamic partitioning that improves runtime and capacity while maintaining SPICE-level accuracy.

What motivated Arm to adopt Cadence's Liberate MX Trio Characterization?

Arm needed a reliable solution to improve accuracy and speed up time to market for its embedded memory IP.