Arteris, Inc. - AIP STOCK NEWS

Arteris (Nasdaq: AIP) and MIPS have announced a partnership to provide a pre-verified reference platform for RISC-V-based SoC designs. The collaboration integrates Arteris' network-on-chip IP, including Ncore cache coherent NoC IP and FlexNoC IP, with MIPS P8700 processor core clusters. This partnership aims to reduce development cycles and risk for chip designs in automotive, enterprise computing, and edge AI applications. The solution supports both homogeneous and heterogeneous architectures, handling AMBA ACE and CHI protocols simultaneously.

Arteris (AIP) reported Q3 2024 financial results with revenue of $14.7 million and achieved record $60.5 million in Annual Contract Value plus royalties, up 6% year-over-year. The company posted a net loss of $7.7 million ($0.20 per share) and Non-GAAP net loss of $3.1 million ($0.08 per share). Remaining performance obligation reached a record $78.4 million, up 25% year-over-year. The company generated positive free cash flow of $1.1 million. For Q4 2024, Arteris expects revenue between $14.7-$15.7 million and ACV plus royalties of $63.0-$67.0 million.

Arteris announced that Tenstorrent has licensed its network-on-chip (NoC) IP for on-chip connectivity in its chiplet-based products. The FlexNoC interconnect technology will be used in Tenstorrent's next generation of AI computing solutions, focusing on high-performance, energy-efficient computing for AI, HPC, and automotive applications. FlexNoC features include congestion management, quality of service, and error detection, enabling low-latency communication between CPU clusters.

Arteris (Nasdaq: AIP) announced that TIER IV has licensed its FlexNoC 5 interconnect IP and Magillem Connectivity SoC integration automation software for next-generation intelligent vehicle electronics. TIER IV will utilize FlexNoC 5 for architectural exploration during development stages and deploy Magillem Connectivity to automatically connect verification IPs and build verification environments for functional safety. The implementation aims to accelerate project timelines while meeting automotive functional safety and performance requirements for autonomous driving systems.

Arteris (Nasdaq: AIP), a leading provider of system IP for SoC creation, has announced that it will release its financial results for the third quarter ended September 30, 2024, after market close on Tuesday, November 5, 2024. The company will host a conference call on the same day at 4:30 PM ET to discuss the results.

Interested parties can join the call by dialing:

• United States/Canada Toll Free: +1-800-717-1738
• International Toll: +1-646-307-1865

Arteris and SiFive have announced a pre-verified solution for the datacenter market, combining Arteris Ncore cache coherent interconnect IP with SiFive P870-D processors. This collaboration aims to reduce project risk and accelerate SoC development for high-performance applications in datacenter and embedded systems markets.

The solution addresses demanding AI workload requirements, offering high compute density and scalability. SiFive's P870-D CPU supports the open AMBA CHI protocol, allowing customers to scale cluster numbers for improved performance while minimizing power consumption. Arteris Ncore IP provides a configurable and scalable network-on-chip interconnect for heterogeneous cache coherent SoCs.

This partnership aims to enable faster, low-risk development cycles for datacenter SoCs with high-performance AI workload and power efficiency requirements.

Arteris, Inc. (Nasdaq: AIP) has announced an innovative evolution of its network-on-chip (NoC) IP products with tiling capabilities and extended mesh topology support for faster development of AI and ML compute in SoC designs. This new functionality enables design teams to scale compute performance by more than 10 times while meeting project schedules and PPA goals.

Key benefits include:

• Scalable Performance: Easily scale systems-on-chip with AI by more than 10 times without changing the basic design
• Power Reduction: Network-on-chip tiles can be turned off dynamically, cutting power by 20% on average
• Design Reuse: Pre-tested network-on-chip tiles can be reused, cutting SoC integration time by up to 50%

The combination of tiling and mesh topologies in Arteris' FlexNoC and Ncore products can reduce XPU sub-system design time and overall SoC connectivity execution time by up to 50% compared to manually integrated, non-tiled designs.

Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP for SoC creation, has announced the addition of Joachim Kunkel to its Board of Directors. Kunkel, former General Manager of Synopsys' IP business unit, brings three decades of experience and a proven track record of growing IP revenue to over $1.5 billion. His expertise in semiconductor intellectual property and leadership is expected to contribute significantly to Arteris' growth strategy.

Kunkel's background includes co-founding CADIS GmbH and holding a master's degree in electrical engineering from Aachen University of Technology. He expressed enthusiasm about joining Arteris at a time when AI is driving complexity in SoC designs, emphasizing the importance of system IP in product performance and innovation cycles.

Arteris, Inc. (Nasdaq: AIP) announced that VeriSilicon has licensed its FlexNoC 5 interconnect IP for high-performance data center SoC solutions. The physically aware interconnect IP offers enhanced cost and design efficiency, scalability, and reliability. VeriSilicon, a custom silicon service provider, has a long-standing relationship with Arteris and has successfully implemented their network-on-chip (NoC) interconnect technology in various SoC designs.

FlexNoC 5 enables VeriSilicon to optimize NoC interconnect logic and physical layouts, reducing iterations and accelerating time to market. It handles high-bandwidth data flows, manages communication between multiple cores, and supports additional components without impacting timing closure. This technology empowers VeriSilicon to design data center SoCs with high-performance computing architectures while effectively addressing timing closure and congestion challenges.