Synopsys Powers World's Fastest UCIe-Based Multi-Die Designs with New IP Operating at 40 Gbps

Rhea-AI Summary

Synopsys has announced the industry's first complete UCIe IP solution operating at up to 40 Gbps per pin, addressing the increased compute performance requirements of AI data centers. This solution includes PHY, controller, and verification IP, offering 25% higher bandwidth than the UCIe specification without impacting energy efficiency or silicon footprint. The IP supports both organic substrate and high-density, advanced packaging technologies, providing flexibility for designers.

Key features include:

• Simplified integration with single reference clock
• Silicon health monitoring for enhanced reliability
• Ecosystem interoperability with popular on-chip interconnect fabrics
• Pre-verified design reference flow
• Broad IP solutions for multi-die designs

The Synopsys 40G UCIe IP will be available in late 2024 for multiple foundries and processes.

Positive

• First-to-market with 40G UCIe IP solution, potentially giving Synopsys a competitive edge
• 25% higher bandwidth than UCIe specification without compromising efficiency
• Supports both organic substrate and advanced packaging technologies, offering design flexibility
• Integrated signal integrity monitors and testability features for improved reliability
• Pre-verified design reference flow to streamline customer adoption

Negative

• Product availability not until late 2024, potentially limiting near-term revenue impact
• Dependent on market adoption of UCIe standard and multi-die designs in AI data centers

Insights

Tech Expert

Synopsys' introduction of the industry's first complete 40G UCIe IP solution marks a significant leap in multi-die design capabilities. This advancement addresses the growing demand for higher bandwidth and lower latency in AI data centers. The 25% increase in bandwidth over the UCIe specification, without compromising energy efficiency or silicon footprint, is particularly noteworthy.

The integration of signal integrity monitors and testability features enhances multi-die package reliability, important for complex AI systems. This solution's compatibility with both organic substrate and advanced packaging technologies offers designers unprecedented flexibility. The pre-verified design reference flow and broad IP solutions for multi-die designs further streamline the development process, potentially accelerating time-to-market for next-generation AI hardware.

Market Research Analyst

This announcement positions Synopsys at the forefront of the rapidly evolving AI chip market. The UCIe interconnect standard is gaining traction as the go-to solution for die-to-die connectivity in high-performance computing. By offering the first 40G UCIe IP solution, Synopsys is likely to capture a significant market share in this growing segment.

The collaboration with Samsung Electronics signals strong industry adoption potential. This could lead to increased revenue streams for Synopsys, not just from IP sales but also from related design tools and services. The comprehensive nature of the solution, including controller, PHY and verification IP, may also help Synopsys to lock in customers across their entire design cycle, potentially boosting long-term customer retention and recurring revenue.

Financial Analyst

This technological advancement could significantly impact Synopsys' financial performance. The company's leadership in the 40G UCIe IP space may translate into higher profit margins and increased market share in the lucrative AI chip design market. The timing is opportune, given the explosive growth in AI data centers and the increasing demand for high-performance computing solutions.

Investors should note that while this innovation positions Synopsys favorably, the full financial impact may not be immediate. The IP solution's availability in late 2024 suggests that revenue recognition might start in fiscal year 2025. However, this early announcement could potentially accelerate design wins and pre-orders, positively affecting the company's forward-looking statements and investor sentiment in the near term.

Complete Synopsys 40G UCIe IP Solution Delivers Maximum Bandwidth for Die-to-Die Connectivity in High-Performance AI Data Center Chips

Highlights

• Industry's first complete 40G UCIe IP solution, including controller, PHY, and verification IP, enables fast connectivity between heterogeneous and homogeneous dies
• Synopsys 40G UCIe PHY IP offers 25% higher bandwidth than the UCIe specification without impact on energy efficiency and silicon footprint
• Integrated signal integrity monitors and testability features improve multi-die package reliability and enable in-field monitoring throughout the silicon lifecycle
• Synopsys 40G UCIe IP is built on a silicon-proven architecture with interoperability success in multiple advanced foundry processes

SUNNYVALE, Calif., Sept. 9, 2024 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today announced the industry's first complete UCIe IP solution operating at up to 40 Gbps per pin to address the increased compute performance requirements of the world's fastest AI data centers. The UCIe interconnect, the de facto standard for die-to-die connectivity, is critical for high-bandwidth, low-latency die-to-die connectivity in multi-die packages, enabling more data to travel efficiently across heterogeneous and homogeneous dies, or chiplets, in today's AI data center systems. Synopsys' 40G UCIe IP supports both organic substrate and high-density, advanced packaging technologies to give designers the flexibility to explore the packaging options that best fit their needs. The complete Synopsys 40G UCIe IP solution, including PHY, controller, and verification IP, is a key component of Synopsys' comprehensive and scalable multi-die solution for fast heterogeneous integration from early architecture exploration to manufacturing. 

"Heterogeneous integration with high-bandwidth die-to-die connectivity gives us the opportunity to deliver new memory chiplets with the efficiency needed for data-intensive AI applications," said Jongwoo Lee, vice president of the System LSI IP Development Team at Samsung Electronics. "Leveraging Synopsys' new 40G UCIe IP, we can extend our collaboration to develop industry-leading chiplet solutions for tomorrow's high-performance data centers."

"Launching the industry's first complete 40G UCIe IP solution underscores Synopsys' continued investment in advancing semiconductor innovation," said Michael Posner, vice president of IP product management at Synopsys. "Our active contribution to the UCIe consortium has enabled us to deliver a robust UCIe solution that helps our customers successfully develop and optimize their multi-die designs for high-performance AI computing systems."

Advanced capabilities of the new Synopsys 40G UCIe IP solution include:

• Simplified Solution Eases IP Integration: Single reference clock feature simplifies the clocking architecture and optimizes power. For ease of use and integration, the IP speeds-up die-to-die link initialization without the need to load the firmware.
• Silicon Health Monitoring Enhances Multi-Die Package Reliability: To ensure reliability at the die, die-to-die, and multi-die package levels, Synopsys 40G UCIe IP offers test and silicon lifecycle management (SLM) features. The monitoring, test, and repair IP and integrated signal integrity monitors enable diagnosis and analysis of the multi-die package from in-design to in-field.
• Successful Ecosystem Interoperability: For on-chip interconnect needs of the latest CPUs and GPUs, Synopsys 40G UCIe IP supports the most popular on-chip interconnect fabrics including AXI, CHI chip-to-chip, streaming, PCI Express, and CXL. For successful interoperability, the IP is compliant with the UCIe 1.1 and 2.0 standards, which Synopsys helps to develop and promote as an active member of the UCIe Consortium.
• Pre-Verified Design Reference Flow: The combination of Synopsys UCIe IP and Synopsys 3DIC Compiler, a unified exploration-to-signoff platform, is used in Synopsys' pre-verified design reference flow that includes all the required design collateral such as automated routing flow, interposer studies, and signal integrity analysis.
• Broad IP Solutions for Multi-Die Designs: In addition to UCIe IP and high-speed SerDes, Synopsys offers HBM3 and 3DIO IP to enable high-capacity memory and 3D packaging.

Availability & Additional Resources

The Synopsys 40G UCIe IP will be available in late 2024 for multiple foundries and processes. 

• Web: Synopsys UCIe IP Solution
• Blog: Synopsys Introduces Industry's First 40G UCIe IP Solution to Power High-Performance Multi-Die Designs
• Blog: UCIe 2.0 - Setting the Tone for Chiplet Interoperability

About Synopsys
Catalyzing the era of pervasive intelligence, Synopsys, Inc. (Nasdaq: SNPS) delivers trusted and comprehensive silicon to systems design solutions, from electronic design automation to silicon IP and system verification and validation. We partner closely with semiconductor and systems customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. Learn more at www.synopsys.com.

Editorial Contact
Kelli Wheeler 
Synopsys, Inc. 
(650) 584-5000
corp-pr@synopsys.com 

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SOURCE Synopsys, Inc.

FAQ

What is the bandwidth of Synopsys' new UCIe IP solution?

Synopsys' new UCIe IP solution operates at up to 40 Gbps per pin, which is 25% higher bandwidth than the UCIe specification.

When will Synopsys (SNPS) release the 40G UCIe IP for customer use?

Synopsys (SNPS) plans to make the 40G UCIe IP available in late 2024 for multiple foundries and processes.

What are the key components of Synopsys' 40G UCIe IP solution?

Synopsys' 40G UCIe IP solution includes PHY, controller, and verification IP, forming a complete package for die-to-die connectivity in multi-die designs.

How does Synopsys' 40G UCIe IP enhance multi-die package reliability?

The IP includes integrated signal integrity monitors and testability features that enable diagnosis and analysis of multi-die packages from in-design to in-field, enhancing overall reliability.