Synopsys Powers World's Fastest UCIe-Based Multi-Die Designs with New IP Operating at 40 Gbps
Synopsys has announced the industry's first complete UCIe IP solution operating at up to 40 Gbps per pin, addressing the increased compute performance requirements of AI data centers. This solution includes PHY, controller, and verification IP, offering 25% higher bandwidth than the UCIe specification without impacting energy efficiency or silicon footprint. The IP supports both organic substrate and high-density, advanced packaging technologies, providing flexibility for designers.
Key features include:
- Simplified integration with single reference clock
- Silicon health monitoring for enhanced reliability
- Ecosystem interoperability with popular on-chip interconnect fabrics
- Pre-verified design reference flow
- Broad IP solutions for multi-die designs
Synopsys ha annunciato la prima soluzione completa di IP UCIe del settore che opera fino a 40 Gbps per pin, rispondendo alle crescenti esigenze di prestazioni di calcolo dei data center AI. Questa soluzione include PHY, controller e IP di verifica, offrendo una larghezza di banda superiore del 25% rispetto alla specifica UCIe senza compromettere l'efficienza energetica o l'ingombro del silicio. L'IP supporta sia substrati organici che tecnologie di imballaggio avanzato ad alta densità, offrendo flessibilità per i progettisti.
Le caratteristiche principali includono:
- Integrazione semplificata con un singolo clock di riferimento
- Monitoraggio della salute del silicio per una maggiore affidabilità
- Interoperabilità dell'ecosistema con popolari tessuti di interconnessione on-chip
- Flusso di design di riferimento pre-verificato
- Soluzioni IP ampie per design multi-die
Synopsys ha anunciado la primera solución completa de IP UCIe de la industria que opera a hasta 40 Gbps por pin, abordando las crecientes demandas de rendimiento de computación de los centros de datos de IA. Esta solución incluye PHY, controlador y IP de verificación, ofreciendo un 25% más de ancho de banda que la especificación UCIe sin afectar la eficiencia energética o la huella de silicio. La IP admite tanto sustratos orgánicos como tecnologías de embalaje avanzado de alta densidad, proporcionando flexibilidad a los diseñadores.
Las características clave incluyen:
- Integración simplificada con un solo reloj de referencia
- Monitoreo de la salud del silicio para una mayor confiabilidad
- Interoperabilidad del ecosistema con tejidos de interconexión on-chip populares
- Flujo de diseño de referencia pre-verificado
- Amplias soluciones de IP para diseños de múltiples chips
Synopsys는 핀당 최대 40 Gbps에서 작동하는 업계 최초의 완전한 UCIe IP 솔루션을 발표하며 AI 데이터 센터의 증가된 컴퓨팅 성능 요구 사항을 수용합니다. 이 솔루션은 PHY, 컨트롤러 및 검증 IP를 포함하여 UCIe 사양보다 25% 더 높은 대역폭을 제공하되 에너지 효율성이나 실리콘 풋프린트에는 영향을 미치지 않습니다. 이 IP는 유기 기판과 고밀도, 첨단 패키징 기술을 모두 지원하여 설계자에게 유연성을 제공합니다.
주요 특징은 다음과 같습니다:
- 단일 기준 클락으로 통합 용이성
- 신뢰성을 높이기 위한 실리콘 상태 모니터링
- 인기 있는 칩 내 인터커넥트 패브릭과의 생태계 상호운용성
- 사전 검증된 디자인 레퍼런스 흐름
- 다중 다이 설계를 위한 광범위한 IP 솔루션
Synopsys a annoncé la première solution complète d'IP UCIe de l'industrie fonctionnant jusqu'à 40 Gbps par broche, répondant aux exigences croissantes en matière de performance de calcul des centres de données IA. Cette solution comprend PHY, contrôleur et IP de vérification, offrant un débit 25 % supérieur à la spécification UCIe sans compromettre l'efficacité énergétique ni l'empreinte silicium. L'IP prend en charge à la fois les substrats organiques et les technologies d'emballage avancé haute densité, offrant de la flexibilité aux concepteurs.
Les principales caractéristiques incluent :
- Intégration simplifiée avec une seule horloge de référence
- Surveillance de la santé du silicium pour une fiabilité accrue
- Interopérabilité de l'écosystème avec des tissus d'interconnexion sur puce populaires
- Flux de conception de référence pré-vérifié
- Solutions IP étendues pour des conceptions multi-die
Synopsys hat die erste vollständige UCIe IP-Lösung der Branche bekannt gegeben, die mit bis zu 40 Gbps pro Pin arbeitet, um den gestiegenen Anforderungen an die Rechenleistung von KI-Datenzentren gerecht zu werden. Diese Lösung umfasst PHY, Controller und Verifizierungs-IP und bietet eine um 25 % höhere Bandbreite als die UCIe-Spezifikation, ohne die Energieeffizienz oder den Siliziumfußabdruck zu beeinträchtigen. Die IP unterstützt sowohl organische Substrate als auch fortschrittliche Verpackungstechnologien mit hoher Dichte und bietet Designern Flexibilität.
Zu den wichtigsten Funktionen gehören:
- Vereinfachte Integration mit einem einzigen Referenztakt
- Silizium-Gesundheitsüberwachung für verbesserte Zuverlässigkeit
- Ökosysteminteroperabilität mit beliebten internen Verbindungsgeweben
- Vorverifiziertes Design-Referenz-Flow
- Breite IP-Lösungen für Multi-Dies-Designs
- First-to-market with 40G UCIe IP solution, potentially giving Synopsys a competitive edge
- 25% higher bandwidth than UCIe specification without compromising efficiency
- Supports both organic substrate and advanced packaging technologies, offering design flexibility
- Integrated signal integrity monitors and testability features for improved reliability
- Pre-verified design reference flow to streamline customer adoption
- Product availability not until late 2024, potentially limiting near-term revenue impact
- Dependent on market adoption of UCIe standard and multi-die designs in AI data centers
Insights
Synopsys' introduction of the industry's first complete 40G UCIe IP solution marks a significant leap in multi-die design capabilities. This advancement addresses the growing demand for higher bandwidth and lower latency in AI data centers. The 25% increase in bandwidth over the UCIe specification, without compromising energy efficiency or silicon footprint, is particularly noteworthy.
The integration of signal integrity monitors and testability features enhances multi-die package reliability, important for complex AI systems. This solution's compatibility with both organic substrate and advanced packaging technologies offers designers unprecedented flexibility. The pre-verified design reference flow and broad IP solutions for multi-die designs further streamline the development process, potentially accelerating time-to-market for next-generation AI hardware.
This announcement positions Synopsys at the forefront of the rapidly evolving AI chip market. The UCIe interconnect standard is gaining traction as the go-to solution for die-to-die connectivity in high-performance computing. By offering the first 40G UCIe IP solution, Synopsys is likely to capture a significant market share in this growing segment.
The collaboration with Samsung Electronics signals strong industry adoption potential. This could lead to increased revenue streams for Synopsys, not just from IP sales but also from related design tools and services. The comprehensive nature of the solution, including controller, PHY and verification IP, may also help Synopsys to lock in customers across their entire design cycle, potentially boosting long-term customer retention and recurring revenue.
This technological advancement could significantly impact Synopsys' financial performance. The company's leadership in the 40G UCIe IP space may translate into higher profit margins and increased market share in the lucrative AI chip design market. The timing is opportune, given the explosive growth in AI data centers and the increasing demand for high-performance computing solutions.
Investors should note that while this innovation positions Synopsys favorably, the full financial impact may not be immediate. The IP solution's availability in late 2024 suggests that revenue recognition might start in fiscal year 2025. However, this early announcement could potentially accelerate design wins and pre-orders, positively affecting the company's forward-looking statements and investor sentiment in the near term.
Complete Synopsys 40G UCIe IP Solution Delivers Maximum Bandwidth for Die-to-Die Connectivity in High-Performance AI Data Center Chips
Highlights
- Industry's first complete 40G UCIe IP solution, including controller, PHY, and verification IP, enables fast connectivity between heterogeneous and homogeneous dies
- Synopsys 40G UCIe PHY IP offers
25% higher bandwidth than the UCIe specification without impact on energy efficiency and silicon footprint - Integrated signal integrity monitors and testability features improve multi-die package reliability and enable in-field monitoring throughout the silicon lifecycle
- Synopsys 40G UCIe IP is built on a silicon-proven architecture with interoperability success in multiple advanced foundry processes
"Heterogeneous integration with high-bandwidth die-to-die connectivity gives us the opportunity to deliver new memory chiplets with the efficiency needed for data-intensive AI applications," said Jongwoo Lee, vice president of the System LSI IP Development Team at Samsung Electronics. "Leveraging Synopsys' new 40G UCIe IP, we can extend our collaboration to develop industry-leading chiplet solutions for tomorrow's high-performance data centers."
"Launching the industry's first complete 40G UCIe IP solution underscores Synopsys' continued investment in advancing semiconductor innovation," said Michael Posner, vice president of IP product management at Synopsys. "Our active contribution to the UCIe consortium has enabled us to deliver a robust UCIe solution that helps our customers successfully develop and optimize their multi-die designs for high-performance AI computing systems."
Advanced capabilities of the new Synopsys 40G UCIe IP solution include:
- Simplified Solution Eases IP Integration: Single reference clock feature simplifies the clocking architecture and optimizes power. For ease of use and integration, the IP speeds-up die-to-die link initialization without the need to load the firmware.
- Silicon Health Monitoring Enhances Multi-Die Package Reliability: To ensure reliability at the die, die-to-die, and multi-die package levels, Synopsys 40G UCIe IP offers test and silicon lifecycle management (SLM) features. The monitoring, test, and repair IP and integrated signal integrity monitors enable diagnosis and analysis of the multi-die package from in-design to in-field.
- Successful Ecosystem Interoperability: For on-chip interconnect needs of the latest CPUs and GPUs, Synopsys 40G UCIe IP supports the most popular on-chip interconnect fabrics including AXI, CHI chip-to-chip, streaming, PCI Express, and CXL. For successful interoperability, the IP is compliant with the UCIe 1.1 and 2.0 standards, which Synopsys helps to develop and promote as an active member of the UCIe Consortium.
- Pre-Verified Design Reference Flow: The combination of Synopsys UCIe IP and Synopsys 3DIC Compiler, a unified exploration-to-signoff platform, is used in Synopsys' pre-verified design reference flow that includes all the required design collateral such as automated routing flow, interposer studies, and signal integrity analysis.
- Broad IP Solutions for Multi-Die Designs: In addition to UCIe IP and high-speed SerDes, Synopsys offers HBM3 and 3DIO IP to enable high-capacity memory and 3D packaging.
Availability & Additional Resources
The Synopsys 40G UCIe IP will be available in late 2024 for multiple foundries and processes.
- Web: Synopsys UCIe IP Solution
- Blog: Synopsys Introduces Industry's First 40G UCIe IP Solution to Power High-Performance Multi-Die Designs
- Blog: UCIe 2.0 - Setting the Tone for Chiplet Interoperability
About Synopsys
Catalyzing the era of pervasive intelligence, Synopsys, Inc. (Nasdaq: SNPS) delivers trusted and comprehensive silicon to systems design solutions, from electronic design automation to silicon IP and system verification and validation. We partner closely with semiconductor and systems customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. Learn more at www.synopsys.com.
Editorial Contact
Kelli Wheeler
Synopsys, Inc.
(650) 584-5000
corp-pr@synopsys.com
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SOURCE Synopsys, Inc.
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