Synopsys IC Compiler II Delivers First-Pass Silicon Success for Graphcore's Multi-Billion Gate AI Processor

Rhea-AI Summary

Synopsys (Nasdaq: SNPS) announced that Graphcore successfully achieved first-pass silicon for its Colossus MK2 GC200 Intelligence Processing Unit (IPU), utilizing Synopsys' IC Compiler II. This advanced AI processor, built on a 7nm process technology, features over 59 billion transistors and 1,472 independent processor cores. The collaboration highlights Synopsys' leadership in digital design solutions, enhancing performance, power, and area metrics significantly. Graphcore's success emphasizes the capabilities of Synopsys' tools in handling complex AI designs, reinforcing their market position.

Positive

• Graphcore achieved first-pass silicon success for its Colossus MK2 GC200 IPU using Synopsys IC Compiler II, enhancing market credibility.
• The IPU features over 59 billion transistors and 1,472 independent processor cores, showcasing significant technological advancement.
• Synopsys' RTL-to-GDS flow and optimization technologies delivered superior performance, power, and area metrics.

Negative

• None.

MOUNTAIN VIEW, Calif., Oct. 12, 2020 /PRNewswire/ --

Highlights

• IC Compiler II, part of the Synopsys Fusion Platform, with its industry-leading capacity and throughput, accelerated implementation of the massive Colossus IPU, exceeding 59 billion transistors
• Innovative optimization technologies for AI-hardware design in the Synopsys RTL-to-GDS flow delivered best-in-class performance, power and areas (PPA) metrics
• Integrated golden signoff technologies delivered predictable and convergent design closure with a zero-margin flow

Synopsys, Inc. (Nasdaq: SNPS) today announced that Graphcore achieved first-pass silicon success using the industry-leading IC Compiler^™ II place-and-route solution, part of the Synopsys Fusion Platform, for designing its second-generation Colossus MK2 GC200 Intelligence Processing Unit (IPU), featuring 59.4 billion transistors, on an industry-leading 7nm advanced process technology. Graphcore leveraged Synopsys IC Compiler II ultra-high capacity architecture and innovative technologies for AI-hardware design resulting in an accelerated implementation of their massive AI processor. Synopsys' RTL-to-GDS flow with state-of-the-art power optimization capabilities along with embedded golden signoff technologies like PrimeTime^® delay calculator, provided Graphcore design teams superior out-of-the-box PPA metrics, and the fastest design closure.

"Synopsys's digital full-flow solution with its best-in-class RTL-to-GDS tools, including Design Compiler^® and IC Compiler II, offers the most comprehensive single-vendor platform, critical to the on-schedule tape out of our latest Colossus IPU," said Phil Horsfield, vice president of Silicon at Graphcore. "Our long-standing relationship with Synopsys has enabled us to leverage state-of-the-art technologies from IC Compiler II and exceed the performance/power targets of this advanced AI processor. We are confident that continued collaboration with Synopsys on IC Compiler II and Fusion Compiler^™ will enable us to push the boundaries of machine intelligence compute."  

The second-generation Colossus GC200 IPU from Graphcore is a sophisticated chip, integrating 1,472 independent processor cores and more than 900 megabytes of on-chip memory to deliver superior parallel processing power for data-center scale AI applications. Synopsys' IC Compiler II, with its AI-design focused capabilities, includes top-level interconnect planning, logic restructuring, congestion-driven mux optimization and full-flow concurrent clock and data optimization delivers best-in-class PPA for the highly repetitive, MAC-based topologies typical in complex AI accelerator chips. Further, its native, high-capacity data model with adaptive abstraction and distributed implementation can efficiently handle multi-billion instance designs with quick turn-around-time. With a unique, golden signoff engine backbone, IC Compiler II delivers highest correlation and hyper-convergent design, to further accelerate design turnaround time.

"The design complexity boundaries of AI compute are continuing to be pushed to its limits, such as with Graphcore's introduction of its latest Colossus IPU," said Neeraj Kaul, vice president of Engineering, Design Group at Synopsys. "Its success in leveraging the latest, AI-optimized technologies in IC Compiler II to simultaneously meet the multiple aggressive design targets for their most complex chip reinforces our leadership position as the place-and-route tool of choice for next-generation, AI designs."

Learn more details about this complex AI Chip as Phil Horsfield, vice president of Silicon at Graphcore, will be presenting on October 14 at the upcoming Synopsys Digital Design Technology Symposium.  For more information regarding Synopsys products, visit: https://www.synopsys.com/implementation-and-signoff.html.

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software^™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.

Editorial Contact:
Simone Souza
Synopsys, Inc.
650-584-6454
simone@synopsys.com 

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SOURCE Synopsys, Inc.

FAQ

What achievement did Synopsys announce regarding Graphcore and its Colossus MK2 GC200 IPU?

Synopsys announced that Graphcore achieved first-pass silicon success for its Colossus MK2 GC200 IPU using Synopsys IC Compiler II.

How many transistors does the Colossus MK2 GC200 IPU contain?

The Colossus MK2 GC200 IPU contains over 59 billion transistors.

What technology did Graphcore use in the design of its latest AI processor?

Graphcore used Synopsys IC Compiler II as part of the Synopsys Fusion Platform for designing its latest AI processor.

What is the significance of the collaboration between Synopsys and Graphcore?

The collaboration underscores Synopsys' leadership in digital design solutions and its ability to handle complex AI designs, improving performance and efficiency.