Synopsys and GLOBALFOUNDRIES Collaborate to Develop Broad Portfolio of DesignWare IP for 12LP+ FinFET Solution
Synopsys (Nasdaq: SNPS) announced a collaboration with GLOBALFOUNDRIES (GF) to develop a comprehensive portfolio of DesignWare IP for GF's advanced 12LP+ FinFET solution. This partnership will enhance high-bandwidth connectivity for cloud computing and AI applications. The 12LP+ technology delivers a 20% improvement in logic performance and a 10% reduction in logic area compared to the previous 12LP solution. DesignWare IP components will be available throughout 2020 and early 2021 to support various applications, including high-performance computing and aerospace.
- Collaboration with GLOBALFOUNDRIES to develop DesignWare IP for GF's 12LP+ solution.
- 12LP+ technology provides a 20% logic performance boost over the previous 12LP platform.
- 10% improvement in logic area scaling for more efficient designs.
- DesignWare IP aimed at enhancing cloud computing and AI chip capabilities.
- Broader IP portfolio supports diverse applications including aerospace and defense.
- None.
MOUNTAIN VIEW, Calif., Sept. 24, 2020 /PRNewswire/ --
Highlights:
- DesignWare IP portfolio for GF 12LP+ solution includes USB4, PCIe 5.0, Die-to-Die HBI and 112G USR/XSR, 112G Ethernet, DDR5, LPDDR5, MIPI, OTP NVM and more
- Long-standing collaboration between the two companies has resulted in the successful development of DesignWare IP from 180-nm to 12-nm for a wide range of applications
Synopsys, Inc. (Nasdaq: SNPS) today announced its collaboration with GLOBALFOUNDRIES® (GF®) to develop a broad portfolio of DesignWare® IP for GF's 12LP+ FinFET solution, including USB4/3.2/DPTX/3.0/2.0, PCIe 5.0/4.0/2.1, die-to-die HBI and 112G USR/XSR, 112G Ethernet, DDR5/4, LPDDR5/4/4X, MIPI M-PHY, Analog-to-Digital Converter, and one-time programmable (OTP) non-volatile memory (NVM) IP. The DesignWare IP is optimized to meet the high-bandwidth memory throughput and reliable, high-performance connectivity demands of cloud computing and AI chips implemented on GF's 12LP+ solution. This recent collaboration marks another significant milestone of the continuous, successful collaboration between the two companies.
GF's most advanced FinFET solution, 12LP+ builds upon GF's established 14nm/12LP platform, of which GF has shipped more than one million wafers. Driving the enhanced performance of 12LP+ are features including a 20-percent SoC-level logic performance boost over 12LP, and a 10-percent improvement in logic area scaling.
"With an excellent combination of performance, power and area, our 12LP+ solution is engineered to meet the specific needs of HPC, cloud and edge AI accelerators, storage, and aerospace and defense applications," said Mark Ireland, vice president of ecosystem and design solutions at GF. "By collaborating with Synopsys, a leading IP provider, on the development of a wide range of high-quality DesignWare IP optimized on GF's 12LP + solution, we are providing greater differentiation and increased value for our mutual customers while minimizing their development costs and speeding their time to market. With Die-to-Die IP, we extend the support to customers who are transitioning to chiplet architectures and seeking a lower product cost and added configuration flexibility."
"As a trusted IP provider, Synopsys continues to make significant investment in collaborating with key foundries such as GF to provide high-quality DesignWare IP on the latest process technologies, so designers can benefit from the performance, power and area improvements," said John Koeter, senior vice president of marketing and strategy for IP at Synopsys. "Our longstanding collaboration with GF through many decades has provided designers with the industry's broadest IP portfolio for GF technologies, including the 12LP+ solution, enabling them to integrate the latest generation of IP required for the fast-growing high-performance computing, AI accelerators for cloud and Edge, as well as the storage, aerospace and defense markets."
Availability
- The silicon design kit for the DesignWare PCIe 5.0, PCIe 2.1 is available now.
- The silicon design kit for DesignWare USB4/3.2/DPTX/3.0/2.0, PCIe 4.0, LPDDR4X multiPHY, Die-to-Die HBI and 112G USR/XSR, 112G Ethernet, MIPI M-PHY and Analog IP are scheduled to be available in the second half of 2020.
- The silicon design kit for DDR5/4, LPDDR5/4/4X, and the preliminary design kit for DesignWare OTP NVM IP are scheduled to be available in Q1 of 2021.
About DesignWare IP
Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, wired and wireless interface IP, security IP, embedded processors and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys' IP Accelerated initiative offers IP prototyping kits, IP software development kits and IP subsystems. Synopsys' extensive investment in IP quality, comprehensive technical support and robust IP development methodology enable designers to reduce integration risk and accelerate time-to-market. For more information on DesignWare IP, visit http://www.synopsys.com/designware.
About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.
Editorial Contacts:
Kelly James
Synopsys, Inc.
650-584-8972
kellyj@synopsys.com
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SOURCE Synopsys, Inc.
FAQ
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