Marvell Demonstrates Industry's Leading 2nm Silicon for Accelerated Infrastructure
Marvell Technology (NASDAQ: MRVL) has unveiled its first 2nm silicon IP platform for next-generation AI and cloud infrastructure, produced on TSMC's 2nm process. The platform includes advanced features such as high-speed 3D I/O for vertically stacking die inside chiplets, with bi-directional I/O operating at speeds up to 6.4 Gbits/second.
The company's platform strategy focuses on developing semiconductor IP components including SerDes, die-to-die interconnects, silicon photonics, and compute fabric interfaces. These serve as building blocks for custom AI accelerators, CPUs, and networking solutions.
Notable market projections indicate custom silicon is expected to represent approximately 25% of the accelerated compute market by 2028, with a 45% annual TAM growth. The new bi-directional I/O technology enables up to 2x bandwidth increase or 50% reduction in connections, particularly beneficial as an estimated 30% of advanced node processors are expected to utilize chiplet designs.
Marvell Technology (NASDAQ: MRVL) ha presentato la sua prima piattaforma di IP in silicio a 2nm per l'infrastruttura AI e cloud di nuova generazione, prodotta con il processo a 2nm di TSMC. La piattaforma include funzionalità avanzate come l'I/O 3D ad alta velocità per la sovrapposizione verticale dei die all'interno dei chiplet, con I/O bidirezionali che operano a velocità fino a 6,4 Gbit/secondo.
La strategia della piattaforma dell'azienda si concentra sullo sviluppo di componenti IP per semiconduttori, tra cui SerDes, interconnessioni die-to-die, fotonica in silicio e interfacce di fabric di calcolo. Questi fungono da mattoni per acceleratori AI personalizzati, CPU e soluzioni di rete.
Proiezioni di mercato notevoli indicano che il silicio personalizzato dovrebbe rappresentare circa il 25% del mercato del calcolo accelerato entro il 2028, con una crescita annuale del TAM del 45%. La nuova tecnologia di I/O bidirezionale consente un aumento della larghezza di banda fino a 2 volte o una riduzione del 50% nelle connessioni, particolarmente vantaggiosa poiché si stima che circa il 30% dei processori a nodo avanzato utilizzeranno design a chiplet.
Marvell Technology (NASDAQ: MRVL) ha presentado su primera plataforma de IP de silicio de 2nm para la infraestructura de IA y nube de próxima generación, producida con el proceso de 2nm de TSMC. La plataforma incluye características avanzadas como I/O 3D de alta velocidad para apilar verticalmente los die dentro de los chiplets, con I/O bidireccional que opera a velocidades de hasta 6.4 Gbits/segundo.
La estrategia de plataforma de la compañía se centra en el desarrollo de componentes de IP de semiconductores, incluidos SerDes, interconexiones die-to-die, fotónica de silicio e interfaces de tejido de computación. Estos sirven como bloques de construcción para aceleradores de IA personalizados, CPUs y soluciones de red.
Proyecciones de mercado notables indican que el silicio personalizado se espera que represente aproximadamente el 25% del mercado de computación acelerada para 2028, con un crecimiento anual del TAM del 45%. La nueva tecnología de I/O bidireccional permite un aumento de ancho de banda de hasta 2 veces o una reducción del 50% en las conexiones, especialmente beneficioso ya que se estima que aproximadamente el 30% de los procesadores de nodo avanzado utilizarán diseños de chiplet.
Marvell Technology (NASDAQ: MRVL)는 TSMC의 2nm 공정으로 생산된 차세대 AI 및 클라우드 인프라를 위한 첫 번째 2nm 실리콘 IP 플랫폼을 공개했습니다. 이 플랫폼은 칩렛 내부에서 다이를 수직으로 쌓기 위한 고속 3D I/O와 최대 6.4 Gbits/초의 속도로 작동하는 양방향 I/O와 같은 고급 기능을 포함합니다.
회사의 플랫폼 전략은 SerDes, 다이 간 인터커넥트, 실리콘 포토닉스 및 컴퓨트 패브릭 인터페이스를 포함한 반도체 IP 구성 요소 개발에 중점을 두고 있습니다. 이들은 맞춤형 AI 가속기, CPU 및 네트워킹 솔루션을 위한 기본 빌딩 블록 역할을 합니다.
주목할 만한 시장 전망에 따르면 맞춤형 실리콘은 2028년까지 가속 컴퓨팅 시장의 약 25%를 차지할 것으로 예상되며, 연간 TAM 성장률은 45%에 이를 것으로 보입니다. 새로운 양방향 I/O 기술은 최대 2배의 대역폭 증가 또는 50%의 연결 감소를 가능하게 하여, 고급 노드 프로세서의 약 30%가 칩렛 디자인을 사용할 것으로 예상되는 점에서 특히 유리합니다.
Marvell Technology (NASDAQ: MRVL) a dévoilé sa première plateforme IP en silicium de 2nm pour l'infrastructure AI et cloud de nouvelle génération, produite selon le processus de 2nm de TSMC. La plateforme comprend des fonctionnalités avancées telles que l'I/O 3D haute vitesse pour empiler verticalement les die à l'intérieur des chiplets, avec un I/O bidirectionnel fonctionnant à des vitesses allant jusqu'à 6,4 Gbit/seconde.
La stratégie de plateforme de l'entreprise se concentre sur le développement de composants IP pour semi-conducteurs, y compris SerDes, interconnexions die-to-die, photonique en silicium et interfaces de tissu de calcul. Ceux-ci servent de blocs de construction pour des accélérateurs AI personnalisés, des CPU et des solutions de mise en réseau.
Des projections de marché notables indiquent que le silicium personnalisé devrait représenter environ 25% du marché du calcul accéléré d'ici 2028, avec une croissance annuelle du TAM de 45%. La nouvelle technologie I/O bidirectionnelle permet une augmentation de la bande passante jusqu'à 2 fois ou une réduction de 50% des connexions, ce qui est particulièrement bénéfique étant donné qu'environ 30% des processeurs à nœud avancé devraient utiliser des conceptions de chiplet.
Marvell Technology (NASDAQ: MRVL) hat seine erste 2nm Silizium-IP-Plattform für die nächste Generation von KI- und Cloud-Infrastrukturen vorgestellt, die im 2nm-Prozess von TSMC produziert wird. Die Plattform umfasst fortschrittliche Funktionen wie hochgeschwindigkeitsfähige 3D-I/O zur vertikalen Stapelung von Dies innerhalb von Chiplets, mit bidirektionalem I/O, das Geschwindigkeiten von bis zu 6,4 Gbit/s erreicht.
Die Plattformstrategie des Unternehmens konzentriert sich auf die Entwicklung von Halbleiter-IP-Komponenten, einschließlich SerDes, Die-to-Die-Interkonnektionen, Siliziumphotonik und Compute-Fabric-Schnittstellen. Diese dienen als Bausteine für maßgeschneiderte KI-Beschleuniger, CPUs und Netzwerklösungen.
Bemerkenswerte Marktprognosen deuten darauf hin, dass maßgeschneidertes Silizium bis 2028 etwa 25% des Marktes für beschleunigtes Rechnen ausmachen wird, mit einem jährlichen TAM-Wachstum von 45%. Die neue bidirektionale I/O-Technologie ermöglicht eine Verdopplung der Bandbreite oder eine Reduzierung der Verbindungen um 50%, was besonders vorteilhaft ist, da geschätzt wird, dass etwa 30% der fortschrittlichen Knotenprozessoren Chiplet-Designs verwenden werden.
- First-to-market with 2nm silicon platform demonstration
- New bi-directional I/O technology doubles bandwidth potential
- Strong market growth projection of 45% annual TAM
- Expected 25% market share in accelerated compute by 2028
- High dependence on TSMC for manufacturing process
- Complex chiplet design requirements for advanced node processors
Insights
Marvell's demonstration of 2nm silicon IP represents a critical technological milestone in the company's platform strategy for next-generation AI and cloud infrastructure. Following their previous advancements with 5nm (2020) and 3nm (2022) platforms, this positions Marvell at the leading edge of semiconductor process technology for data infrastructure.
The announcement highlights strategic significance for investors in three key areas:
- Market opportunity in custom silicon, projected to grow at
45% annually and capture25% of the accelerated compute market by 2028 - Technological differentiation through advanced 3D simultaneous bi-directional I/O that can double bandwidth or reduce connections by
50% - Deepened partnership with TSMC securing access to industry-leading process technology
This technology demonstration addresses evolving hyperscaler requirements for custom accelerated infrastructure in the AI era. The bi-directional I/O innovation is particularly notable as it enables more complex chiplet designs - critically important as
Marvell's platform approach, leveraging a portfolio of semiconductor IP including SerDes, die-to-die interconnects, and silicon photonics, strengthens their position in the custom silicon value chain for AI infrastructure. This demonstration signals Marvell's commitment to maintaining leadership in advanced node technology for data infrastructure, potentially expanding their addressable market in high-growth AI segments.
Marvell's 2nm silicon demonstration represents a significant technical achievement that merits attention for its architectural innovations beyond just the process node advancement. The 3D simultaneous bi-directional I/O operating at 6.4 Gbits/second is particularly groundbreaking, as it fundamentally changes how vertically stacked dies communicate within chiplets.
Current multi-die packages typically utilize unidirectional I/O pathways, creating inherent bandwidth constraints or requiring more physical connections. By enabling bidirectional communication on the same pathway, Marvell addresses two critical challenges in advanced semiconductor design:
- Bandwidth density improvements - potentially doubling data throughput in the same footprint
- Power efficiency gains - fewer I/O pathways likely translates to reduced power consumption
This innovation directly addresses scaling challenges as chips exceed reticle limits. The semiconductor industry's shift toward chiplet designs (projected to reach
Marvell's comprehensive platform approach - developing portfolio technologies like SerDes, die-to-die interconnects, advanced packaging, silicon photonics, and compute architectures - creates a technological foundation that can accelerate development cycles for both their standard products and custom designs. By demonstrating 2nm silicon now, Marvell establishes early expertise with TSMC's most advanced node, potentially gaining competitive advantages in both manufacturing access and design expertise for AI-focused data infrastructure.
- The Marvell® 2nm platform will enable hyperscalers to dramatically boost the performance and efficiency of their infrastructure to meet the performance and efficiency demands of the AI era.
- Built on TSMC's 2nm process, the silicon is a critical part of the Marvell platform for developing next-generation custom AI accelerators, CPUs, and networking.
- The silicon IP includes high-speed 3D I/O for vertically stacking die inside chiplets.
Given a projected
A Building Block Approach
The Marvell platform strategy centers around developing a comprehensive portfolio of semiconductor IP—including electrical and optical serializer/deserializers (SerDes), die-to-die interconnects for 2D and 3D devices, advanced packaging technologies, silicon photonics, custom high-bandwidth memory (HBM) compute architecture, on-chip static random-access memory (SRAM), system-on-chip (SoC) fabrics, and compute fabric interfaces such as PCIe Gen 7—that serve as building blocks for developing custom AI accelerators, CPUs, optical DSPs, high-performance switches and other technologies.
Advanced Technology Leadership
Starting with the launch of the industry's leading 5nm data infrastructure silicon platform in 2020, Marvell has been at the forefront of developing products produced on advanced technology nodes to market. Marvell announced the industry's leading 3nm platform in 2022, with first silicon produced in 2023 and multiple industry standard and custom silicon products now shipping and in development.
"The platform approach enables us to accelerate the development of market-leading high-speed SerDes and other critical technologies on the latest process manufacturing nodes, which in turn enables Marvell and its customers to accelerate the development of XPUs and other accelerated infrastructure technologies," said Sandeep Bharathi, chief development officer at Marvell. "Our longstanding collaboration with TSMC plays a pivotal role in helping Marvell develop complex silicon solutions with industry-leading performance, transistor density and efficiency."
New on the Marvell 2nm Platform
Additionally, Marvell delivered a 3D simultaneous bi-directional I/O operating at speeds up to 6.4 Gbits/second for connecting vertically stacked die inside of chiplets. Today, the I/O pathways connecting stacks of die are typically unidirectional. Shifting to a bi-directional I/O gives designers the ability to increase bandwidth by up to two times and/or reduce the number of connections by
3D simultaneous bi-directional I/O will also give chip designers greater flexibility in design. Today's most advanced chips exceed the size of the reticle, or photomask, for outlining transistor patterns onto silicon. To increase transistor count, an estimated
"TSMC is pleased to collaborate with Marvell on the development of its 2nm platform and the delivery of its first silicon," said Dr. Kevin Zhang, senior vice president of business development and global sales, and deputy co-chief operating officer at TSMC. "We look forward to our continued collaboration with Marvell to utilize TSMC's best-in-class silicon technology process and packaging technologies to advance accelerated infrastructure for the AI era."
About Marvell
To deliver the data infrastructure technology that connects the world, we're building solutions on the most powerful foundation: our partnerships with our customers. Trusted by the world's leading technology companies for over 25 years, we move, store, process and secure the world's data with semiconductor solutions designed for our customers' current needs and future ambitions. Through a process of deep collaboration and transparency, we're ultimately changing the way tomorrow's enterprise, cloud, automotive, and carrier architectures transform—for the better.
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2. Semiconductor Digest and Gartner, December 2024.
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