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GBT Seeks to Develop an AI Empowered Technology for Automatic Compaction of Integrated Circuit Layout Data IPs

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GBT Technologies Inc. (GTCH) is developing an AI-driven technology aimed at compacting integrated circuit (IC) layout blocks. With the semiconductor industry facing complexity and size challenges in microchips, this technology seeks to optimize layouts, reducing silicon area and improving yield. The goal is to automate the design process while maintaining crucial design rules and electrical connectivity. However, the company faces challenges in funding and strategic partnerships for successful implementation. The technology targets various IC styles, promising enhanced performance and reduced costs for the industry.

Positive
  • Development of AI technology for IC layout compaction could reduce silicon area and increase yield.
  • Technology aims to optimize existing design processes, aligning with industry needs for more efficient manufacturing.
Negative
  • No guarantee of successful research, development, or implementation of the technology.
  • Company needs to secure capital and partnerships to bring the technology to market.

Aiming for significant reduction of microchip’s layout blocks area and improved overall silicon yield

SAN DIEGO, Feb. 15, 2022 (GLOBE NEWSWIRE) -- GBT Technologies Inc. (OTC PINK: GTCH ) ("GBT” or the “Company”), is developing an AI empowered technology for automatic compaction of integrated circuit (IC) layout blocks. As modern ICs are ever growing in complexity and size there is a high demand for design automation to reduce silicon area and increase its yield. Microchips are expected to include more functionalities, consuming less power, reducing in size and ultimately cheaper. The semiconductor field is pushing the envelope by introducing smaller manufacturing processes scaling into deep nanometer ranges. Scaling down the manufacturing process enables billions of transistors on die, higher performance, and power consumption reduction, but introduces new design challenges due to complicated physics rules. IC projects may take longer time as they need to comply with a vast amount of complex design rules and constraints. It is the Company’s position that an automatic IC layout compaction technology can be an efficient way to reduce new and existing layout IPs size utilizing less silicon area with the goal of increasing the overall yield.

The main goal of the compaction process is to create the densest IC layout possible. GBT is now designing an AI empowered technology to read existing and new microchip’s layout data with the goal of producing the densest layout block possible. The technology is seeking to optimize post-layout IPs, shrinking them automatically retaining geometrical design rule and electrical connectivity correctness. In addition, a goal of the computer program is to maintain Design for Manufacturing (DFM) constraints to comply with the manufacturing process. The technology design contemplates implementing graph-based optimization algorithms and deep learning training for fast processing and optimal area utilization.

The technology is targeted for Analog, Digital, RF and MIXED integrated circuits styles with the goal of supporting GDSII and Oasis data.

With today’s ever growing microchips size and complexity there is a need for urgent Electronic Design Automation (EDA) solutions to decrease IC’s size and increase performance while decreasing cost. GBT believes that utilizing an intelligent IP block compaction technology may result in achieving these goals.

“Today’s microchips include billions of transistors which make a significant impact on the overall chip’s die size. As larger silicon ‘real-estate’ is, designers have to face more complex electrical and performance challenges. The industry is constantly scaling down the manufacturing process, reaching deep nanometer ranges which introduce more complicated physics-oriented challenges. We believe an efficient layout compaction technology can be a great functional and economical solution for existing and new IP blocks. We are now designing an AI based technology to read an existing IC layout block and compacting its size to the densest possible. The process is targeted to be done automatically and within short time. We are seeking to design the program with the goal of maintaining the process design rules, DFM guidelines and electrical connectivity correctness. It is the goal for the entire silicon area to undergo significant reduction and therefore enable improved silicon yield and ultimately cheaper ICs. The technology is planned to support older and advanced nanometer processes, Analog, Digital, RF and MIXED styles, making it a flexible tool for all types of IC design firms. As Integrated Circuits technology advances, more functionalities, lower power consumption, higher performance and lower cost are in high demand, especially within advanced nanometer projects,” stated Danny Rittman, the Company’s CTO.

There is no guarantee that the Company will be successful in researching, developing or implementing this system. In order to successfully implement this concept, the Company will need to raise adequate capital to support its research and, if successfully researched, developed and granted regulatory approval, the Company would need to enter into a strategic relationship with a third party that has experience in manufacturing, selling and distributing this product. There is no guarantee that the Company will be successful in any or all of these critical steps.

About Us

GBT Technologies, Inc. (OTC PINK: GTCH) (“GBT”) (http://gbtti.com) is a development stage company which considers itself a native of Internet of Things (IoT), Artificial Intelligence (AI) and Enabled Mobile Technology Platforms used to increase IC performance. GBT has assembled a team with extensive technology expertise and is building an intellectual property portfolio consisting of many patents. GBT’s mission, to license the technology and IP to synergetic partners in the areas of hardware and software. Once commercialized, it is GBT’s goal to have a suite of products including smart microchips, AI, encryption, Blockchain, IC design, mobile security applications, database management protocols, with tracking and supporting cloud software (without the need for GPS). GBT envisions this system as a creation of a global mesh network using advanced nodes and super performing new generation IC technology. The core of the system will be its advanced microchip technology; technology that can be installed in any mobile or fixed device worldwide. GBT’s vision is to produce this system as a low cost, secure, private-mesh-network between all enabled devices. Thus, providing shared processing, advanced mobile database management and sharing while using these enhanced mobile features as an alternative to traditional carrier services.

Forward-Looking Statements

Certain statements contained in this press release may constitute "forward-looking statements".  Forward-looking statements provide current expectations of future events based on certain assumptions and include any statement that does not directly relate to any historical or current fact. Actual results may differ materially from those indicated by such forward-looking statements because of various important factors as disclosed in our filings with the Securities and Exchange Commission located at their website (http://www.sec.gov).  In addition to these factors, actual future performance, outcomes, and results may differ materially because of more general factors including (without limitation) general industry and market conditions and growth rates, economic conditions, governmental and public policy changes, the Company’s ability to raise capital on acceptable terms, if at all, the Company’s successful development of its products and the integration into its existing products and the commercial acceptance of the Company’s products.  The forward-looking statements included in this press release represent the Company's views as of the date of this press release and these views could change.  However, while the Company may elect to update these forward-looking statements at some point in the future, the Company specifically disclaims any obligation to do so.  These forward-looking statements should not be relied upon as representing the Company's views as of any date subsequent to the date of the press release.

Contact:
Dr. Danny Rittman, CTO
press@gopherprotocol.com


FAQ

What is GTCH's goal with its new AI technology for IC layout compaction?

GTCH aims to reduce silicon area and improve yield through automated IC layout compaction.

What challenges does GTCH face in developing its AI technology?

GTCH faces challenges in securing capital and establishing strategic partnerships for successful technology implementation.

What types of integrated circuits does GTCH's technology target?

The technology targets Analog, Digital, RF, and MIXED integrated circuit styles.

How does GTCH's technology plan to improve microchip design?

The technology aims to optimize post-layout IPs while maintaining design rules and electrical connectivity.

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