GBT is Researching to Automate IC’s Connectivity Mismatches Correction to Achieve Faster and Better Advanced Nanometer Designs
GBT Technologies Inc. (OTC PINK: GTCH) is advancing automation in integrated circuit (IC) design through the development of an LVS Auto-Correct program, aimed at addressing electrical connectivity mismatches. This project, code-named SIGMA, aims to reduce IC design time from days to minutes for advanced 5nm chips. A provisional patent was filed on September 27, 2021. However, the company notes the lack of guaranteed success in the development process, which will require significant capital and potential partnerships for commercialization.
- Development of LVS Auto-Correct program to automate IC design corrections.
- Provisional patent filed to protect the new technology.
- Significant potential to reduce IC design time from days to minutes.
- No guarantee of success in research, development, or product implementation.
- Need for substantial capital to support ongoing research.
SAN DIEGO, Oct. 05, 2021 (GLOBE NEWSWIRE) -- GBT Technologies Inc. (OTC PINK: GTCH ) ("GBT” or the “Company”), is researching to automate integrated circuits electrical connectivity mismatches correction to achieve faster and more efficient designs; particularly, for advanced nanometer range of 5nm and below. The project’s internal code name is SIGMA. A provisional application was filed on September 27, 2021 in the U.S. Patent and Trademark Office (“USPTO”). The application has been assigned serial number 63248550 with the USPTO.
In the past decade the IC industry has experienced exponential improvements in design and manufacturing domains. As science continues to overcome physics and electrical obstacles, these barriers are constantly moving. An IC design flow comprises of stages which involve software tools that architect, capture, simulate and verify the IC’s correctness. These computer-aided-design (CAD), also called EDA (Electronic Design Automation) are key aspects in transforming product’s definition and circuit concepts into production-ready IC design. One of the must have tools is the Layout-Vs-Schematics computer program (also called LVS verification), which verifies the electrical connectivity of an IC layout against its schematic diagram. Mismatches mean a non-functional chip or wrong electrical functionalities. Typically, in custom and semi-custom IC layout styles, these corrections must be done manually which is a significant time-consuming process. GBT is researching to develop an LVS Auto-Correct computer program for IC layout electrical connectivity mismatch corrections. The system will read an IC’s schematic and layout data, compare their electrical connectivity and in case of mismatches detection, disconnect, and re-route creating a correct electrical connection. The system will take into consideration the process design rules, reliability constraints and DFM (Design for Manufacturing) aspects. GBT believes that such an automation tool will majorly reduce the overall IC’s design time and time to market.
“A typical microchip design process includes many steps. After the IC’s specification and architecture stage, a schematic diagram that represents the integrated circuit is prepared. The schematic diagram provides a representation of the logical connections between the logic elements that form the integrated circuit. Once the schematic diagram has been tested to verify that the circuit performs the correct functions, the schematic diagram is converted into a mask layout database that includes a series of polygons. These polygons may represent the logic elements and the logical connections from the schematic diagram. The mask layout database is then used to form a series of photomasks, also known as masks or reticles, that may be used to manufacture the different layers of the integrated circuit. Typically, the mask layout database is created manually by a mask designer or automatically by a synthesis tool. Once the mask layout database is complete; polygons that form electrical connections in the mask layout database are compared to the logical connections from the schematic diagram. This comparison, called LVS (Layout-vs-Schematic) may result in connection mismatches between the schematic diagram and the mask layout database. A connection mismatch typically, indicates that an electrical connection in the mask layout database does not match its corresponding logical connection in the schematic diagram, which may cause a circuit malfunction or wrong operation. A correction of electrical connectivity mismatches within an IC data can be a significant time-consuming process; especially, with advanced nanometer chips like 5nm and below. These are exponentially growing, and include billions of transistors, which is why we are researching to develop an automated LVS correction system. Such a system will analyze an entire chips data, check for electrical connectivity mismatches, and Auto-Correct them with a click of a button. The correction process will be involved with identifying existing mismatch connections, disconnect them, and re-route correctly. The process is targeted to take minutes, which as typically, takes days to fix manually. We plan to incorporate our neural networks and advanced computational geometry algorithms to achieve these functionalities. We have already filed a provisional patent to protect the project’s system and methods and will file a non-provisional patent in the upcoming months to protect the IP. We firmly believe that such a system can become a significant productivity enhancement tool for all IC design firms; one to significantly, reduce their project’s design times and bringing them faster to the market.” Stated Danny Rittman, the Company’s CTO.
There is no guarantee that the Company will be successful in researching, developing or implementing this system. In order to successfully implement this concept, the Company will need to raise adequate capital to support its research and, if successfully researched, developed and granted regulatory approval, the Company would need to enter into a strategic relationship with a third party that has experience in manufacturing, selling and distributing this product. There is no guarantee that the Company will be successful in any or all of these critical steps.
About Us
GBT Technologies, Inc. (OTC PINK: GTCH) (“GBT”) (http://gbtti.com) is a development stage company which considers itself a native of Internet of Things (IoT), Artificial Intelligence (AI) and Enabled Mobile Technology Platforms used to increase IC performance. GBT has assembled a team with extensive technology expertise and is building an intellectual property portfolio consisting of many patents. GBT’s mission, to license the technology and IP to synergetic partners in the areas of hardware and software. Once commercialized, it is GBT’s goal to have a suite of products including smart microchips, AI, encryption, Blockchain, IC design, mobile security applications, database management protocols, with tracking and supporting cloud software (without the need for GPS). GBT envisions this system as a creation of a global mesh network using advanced nodes and super performing new generation IC technology. The core of the system will be its advanced microchip technology; technology that can be installed in any mobile or fixed device worldwide. GBT’s vision is to produce this system as a low cost, secure, private-mesh-network between all enabled devices. Thus, providing shared processing, advanced mobile database management and sharing while using these enhanced mobile features as an alternative to traditional carrier services.
Forward-Looking Statements
Certain statements contained in this press release may constitute "forward-looking statements". Forward-looking statements provide current expectations of future events based on certain assumptions and include any statement that does not directly relate to any historical or current fact. Actual results may differ materially from those indicated by such forward-looking statements because of various important factors as disclosed in our filings with the Securities and Exchange Commission located at their website (http://www.sec.gov). In addition to these factors, actual future performance, outcomes, and results may differ materially because of more general factors including (without limitation) general industry and market conditions and growth rates, economic conditions, governmental and public policy changes, the Company’s ability to raise capital on acceptable terms, if at all, the Company’s successful development of its products and the integration into its existing products and the commercial acceptance of the Company’s products. The forward-looking statements included in this press release represent the Company's views as of the date of this press release and these views could change. However, while the Company may elect to update these forward-looking statements at some point in the future, the Company specifically disclaims any obligation to do so. These forward-looking statements should not be relied upon as representing the Company's views as of any date subsequent to the date of the press release.
Contact:
Dr. Danny Rittman, CTO
press@gopherprotocol.com
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