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Credo Technology Group to Exhibit at Chiplet Summit 2024

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Credo Technology Group Holding Ltd (CRDO) will be exhibiting at the Chiplet Summit Conference and Exhibition to discuss its chiplet and intellectual property (IP) solutions, including the recent portfolio expansion of the 112G PAM4 SerDes IP family in the latest process technology. Jeff Twombly, Vice President of Business Development, will participate in a panel discussion on the Best Ways to Optimize Chiplets. The summit provides an excellent platform for Credo to engage with the chiplet ecosystem and showcase its offerings.
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SAN JOSE, Calif.--(BUSINESS WIRE)-- Credo Technology Group Holding Ltd (“Credo”) (Nasdaq: CRDO), an innovator in providing secure, high-speed connectivity solutions that deliver improved power efficiency as data rates and corresponding bandwidth requirements increase throughout the data infrastructure market, will be exhibiting in booth 316 at the Chiplet Summit Conference and Exhibition taking place February 6-8, at the Santa Clara Convention Center.

The summit is an excellent platform for Credo representatives to discuss the company’s comprehensive family of chiplet and intellectual property (IP) solutions with the chiplet ecosystem. Attendees are encouraged to visit booth 316 to receive briefings on all Credo’s chiplet offerings including the recent portfolio expansion of the 112G PAM4 SerDes IP family in the latest process technology.

Jeff Twombly, Vice President of Business Development, will also participate in a panel discussion on the Best Ways to Optimize Chiplets.

Panel C-103: Best Ways to Optimize Chiplets
Location: Great America Meeting Room 3
Time: Wednesday, February 7th, 4:30 PST

Session Description: Chiplet optimization may involve many approaches. Power demands can be reduced by lowering voltage levels or reducing operating frequencies. Throughput can be increased by using faster interfaces or shortening distances between devices. Other approaches include using optical interconnect instead of electrical, using faster memory technologies such as MRAM, or avoiding structures such as interposers which slow down signals.

Credo invites all Chiplet Summit attendees to visit booth 316 and attend our panel to learn more.

About Credo

Our mission is to deliver high-speed solutions to break bandwidth barriers on every wired connection in the data infrastructure market. Credo is an innovator in providing secure, high-speed connectivity solutions that deliver improved power efficiency as data rates and corresponding bandwidth requirements increase exponentially throughout the data infrastructure market. Our innovations ease system bandwidth bottlenecks while simultaneously improving on power, security, and reliability. Our connectivity solutions are optimized for optical and electrical Ethernet applications, including the emerging 100G (or Gigabits per second), 200G, 400G, 800G and the emerging 1.6T (or Terabits per second) port markets. Credo products are based on our proprietary Serializer/Deserializer (SerDes) and Digital Signal Processor (DSP) technologies. Our product families include Integrated Circuits (ICs) for the optical and line card markets, Active Electrical Cables (AECs) and SerDes Chiplets. Our intellectual property (IP) solutions consist primarily of SerDes IP licensing.

For more information, please visit https://www.credosemi.com. Follow Credo on LinkedIn.

Media Contact:

Corey Bentley

corey.bentley@credosemi.com



Investor Contact:

Dan O’Neil

dan.oneil@credosemi.com

Source: Credo Technology Group Holding Ltd

FAQ

What is the event that Credo will be participating in?

Credo will be exhibiting at the Chiplet Summit Conference and Exhibition.

What is the ticker symbol for Credo Technology Group Holding Ltd?

The ticker symbol for Credo is CRDO.

Who will participate in the panel discussion at the summit?

Jeff Twombly, Vice President of Business Development, will participate in a panel discussion on the Best Ways to Optimize Chiplets.

What will be discussed at the panel session?

The panel session will focus on chiplet optimization approaches, including reducing power demands, increasing throughput, and using advanced technologies such as MRAM.

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