Cadence Design Systems - CDNS STOCK NEWS

Cadence Design Systems (Nasdaq: CDNS) announced its custom and analog/mixed-signal IC design flow has been certified for Samsung Foundry's 3nm GAA process technology. This certification allows Cadence and Samsung's customers to leverage an automated design, layout, signoff, and verification flow for applications in automotive, mobile, data center, and AI sectors. Key features of the flow include improved productivity through automated constraint-driven layout, advanced circuit verification, and seamless interoperability with digital block implementation. This milestone enhances design capabilities for next-generation products.

Cadence Design Systems reported third quarter 2020 revenue of $667 million, up from $580 million in the same quarter of 2019. The company achieved a GAAP operating margin of 25% and net income of $162 million ($0.58 per share), compared to $102 million ($0.36 per share) a year earlier. Non-GAAP results showed an operating margin of 36% and net income of $197 million ($0.70 per share). Cadence raised its 2020 revenue guidance to $2.643 billion to $2.663 billion and announced stock repurchases of $75 million.

Cadence Design Systems (Nasdaq: CDNS) has launched the Clarity 3D Transient Solver, a powerful system-level simulation tool designed to accelerate electromagnetic interference (EMI) solutions. This product offers up to 10X faster performance compared to traditional 3D field solvers and eliminates the need for costly anechoic test chambers. The technology allows for rapid, large-scale simulations, reducing design cycle times by up to 30% for various markets, including automotive and aerospace. The Clarity 3D Transient Solver supports Cadence's Intelligent System Design strategy and is expected to be available in early 2021.

Cadence Design Systems (Nasdaq: CDNS) launched its new Cadence System-Level Verification IP (System VIP) to enhance system-on-chip (SoC) verification. The suite automates testbench assembly, traffic generation, and performance analysis, achieving up to 10X efficiency in chip-level verification. Key components include the System Testbench Generator, System Traffic Libraries, System Performance Analyzer, and System Verification Scoreboard. The solution extends Cadence’s leadership in IP-level verification to chip-level challenges, ensuring better throughput and quality in complex SoC designs.

Cadence Design Systems (Nasdaq: CDNS) announced that TriEye utilized the Cadence® Spectre® X Simulator to expedite the design of a next-generation CMOS-based Short-Wave Infrared (SWIR) image sensor by several months. TriEye achieved a 2X performance increase over prior simulators while ensuring ISO compliance for automotive applications. The Spectre X Simulator, known for its accuracy in handling complex designs, allowed TriEye to optimize their development process, significantly reducing time to market.

Cadence Design Systems (Nasdaq: CDNS) has announced that its Pegasus Verification System has received certification from TSMC for the N16, N12, and N7 process technologies. This certification allows customers to efficiently achieve physical verification with TSMC-certified rule decks. The system facilitates massive job distribution on various hardware, optimizing performance with TSMC’s advanced processes. This collaboration aims to enhance design cycle efficiency and accuracy for applications in AI, automotive, and data centers.

Cadence Design Systems (Nasdaq: CDNS) announced its silicon-proven Cadence IP for GDDR6 on TSMC’s N6 and N7 processes, with plans for N5 implementation. This Design IP enables high-bandwidth memory applications, crucial for AI, 5G, and hyperscale computing. The GDDR6 architecture offers over 2X the data rate of DDR5 and LPDDR5, achieving 16Gbit/s bandwidth per pin and 512Gbit/s per chip. Cadence's collaboration with TSMC and Micron focuses on enhancing performance and power efficiency for next-gen memory-intensive solutions.

Cadence Design Systems (CDNS) will host a live webcast on October 19, 2020 to discuss its third quarter financial results. The event will feature CEO Lip-Bu Tan and CFO John Wall, starting at 2:00 PM PT. An archive of the webcast will be accessible online from 5:00 PM PT on the same day until December 18, 2020. Cadence continues to lead in electronic design, leveraging over 30 years of software expertise to support innovative companies across various sectors. More details can be found at cadence.com/cadence/investor_relations.