GUC Optimizes Quality of Results and Accelerates Time to Tapeout Using the Cadence Digital Full Flow

Rhea-AI Summary

Cadence Design Systems (CDNS) announced that Global Unichip Corporation (GUC) utilized its Innovus Implementation System to significantly enhance ASIC design efficiency. GUC achieved a 10% reduction in wirelength and 5% improvement in switching power, while reducing floorplan design time from weeks to days. This advancement supports GUC in meeting the rising demands for mobile, automotive, AI, and hyperscale computing applications, particularly as ASIC designs grow in complexity. Cadence remains committed to delivering advanced digital design solutions.

Positive

• Achieved over 10% wirelength reduction.
• Improved switching power by 5%.
• Accelerated floorplan design time from weeks to days.

Negative

• None.

Highlights:

• Cadence’s Innovus Implementation System mixed-placer automation delivers more than 10% wirelength reduction and 5% better switching power
• GUC reduces floorplan design time from weeks to days, accelerating ASIC design creation for mobile, automotive, AI and hyperscale computing applications

SAN JOSE, Calif.--(BUSINESS WIRE)-- Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced Global Unichip Corporation (GUC) used the Cadence^® digital full flow to accelerate the time to tapeout of its ASIC designs for mobile, automotive, AI and hyperscale computing applications. By leveraging the Cadence Innovus^™ Implementation System’s mixed-placer automation technology, GUC successfully reduced floorplan design time from weeks to days and achieved more than 10% reduced wirelength and 5% better switching power.

GUC has been using the Cadence digital full flow for many years to tape out the most challenging ASIC designs down to the latest 5nm and 3nm process nodes. As a leading global ASIC provider, delivering the best power, performance and area (PPA) results within ever more demanding schedules is critical for success.

As ASIC designs grow in size and complexity, the number of macros in a floorplan also increases rapidly, making GUC’s traditional manual and iterative floorplanning process a lengthy part of the implementation schedule. Using the Innovus mixed-placer technology, the GUC team can handle the placement of both standard cells and macros concurrently, automating the floorplanning process to achieve greater efficiency and faster PPA analysis.

“As our ASIC customer designs move to the latest process nodes and grow in size and complexity, GUC is always making strategic investments in the latest technologies that ensure we can meet and exceed customer requirements for optimal PPA,” said Louis Lin, senior vice president at GUC. “Cadence’s Innovus mixed-placer technology enabled us to make a significant productivity breakthrough, so that we could complete customer designs more efficiently and accelerate tapeout. The Innovus mixed-placer technology is now a key part of our GUC production implementation flow, providing many tapeout successes, and we use it for the majority of our designs.”

The Cadence digital full flow provides customers with a fast path to design closure and better predictability. It supports the company’s Intelligent System Design^™ strategy, enabling SoC design excellence. For more information on the digital full flow, please visit www.cadence.com/go/dffpr.

About Cadence

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications, including consumer, hyperscale computing, 5G communications, automotive, mobile, aerospace, industrial and healthcare. For seven years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.

© 2021 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

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Source: Cadence Design Systems, Inc.

FAQ

What are the benefits of Cadence's Innovus Implementation System for ASIC designs?

Cadence's Innovus Implementation System has enabled customers like GUC to achieve over 10% wirelength reduction and 5% better switching power while drastically reducing floorplan design time.

How does Cadence support GUC's ASIC design processes?

Cadence provides a digital full flow that accelerates the design process for ASICs, allowing GUC to tape out designs more efficiently.

What industries benefit from Cadence's digital full flow?

Industries such as mobile, automotive, AI, and hyperscale computing benefit from Cadence's digital full flow by enhancing ASIC design efficiency.

What is the significance of reducing floorplan design time for ASICs?

Reducing floorplan design time allows companies like GUC to accelerate their ASIC design creation, meeting market demands faster.

What process nodes does GUC utilize with Cadence's technology?

GUC has been using Cadence's digital full flow to tape out ASIC designs down to the latest 5nm and 3nm process nodes.