Cadence Delivers 13 New VIP and Expands System VIP Portfolio to Accelerate Automotive, Hyperscale Data Center and Mobile SoC Verification

Rhea-AI Summary

Cadence Design Systems has introduced 13 new Verification IP (VIP) solutions aimed at enhancing the verification process for System-on-Chip (SoC) designs. These offerings support industry standards including Arm AMBA 5 CHI-f, UCIe, GDDR7, and DDR5 DIMM. The new VIP solutions feature a consistent application programming interface (API) and comprehensive coverage models that promise up to 10X efficiency improvements in SoC verification processes. Customers can utilize Cadence's TripleCheck technology for compliance verification and performance analysis. This expansion aligns with Cadence's broader Intelligent System Design strategy.

Positive

• Introduction of 13 new VIP solutions enhances product offerings.
• Supports compliance with the latest industry standards.
• TripleCheck technology improves verification accuracy.
• Promises up to 10X efficiency improvements in SoC verification.

Negative

• None.

New additions enable fast and comprehensive verification, ensuring SoCs meet the latest standard specifications

SAN JOSE, Calif.--(BUSINESS WIRE)-- Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the availability of 13 new Verification IP (VIP) solutions that enable engineers to quickly and effectively verify their designs to meet the specifications for the latest standards protocols. The new Cadence^® VIP offerings empower customers to confidently develop their next-generation automotive, hyperscale data center and mobile SoCs and microcontrollers while keeping pace with the latest industry standards, including Arm^® AMBA^® 5 CHI-f, Universal Chiplet Interconnect Express^™ (UCIe^™), GDDR7, DDR5 DIMM, MIPI^® A-PHY^® and SoundWire^® I3S, and USB4 2.0 interfaces.

The new Cadence VIP offer customers a comprehensive verification solution for the most complex protocols. Cadence customers have access to a consistent application programming interface (API) across all VIP with complete bus function models (BFMs), integrated protocol checks and coverage models, facilitating rapid adoption. The VIP support multiple application areas and specifications, including:

• Hyperscale data center:
  • UCIe
  • AMBA 5 CHI-f
  • DTI
  • Latest version of DDR5 DIMM
• Automotive:
  • MIPI A-PHY 1.1
  • CAN XL
  • Flash ONFI 5.1
• Consumer and mobile:
  • USB4 2.0
  • GDDR7
  • MIPI SoundWire I3S (SWI3S)
  • Latest version of LPDDR
  • DFI
  • HDMI 2.1

All Cadence VIP solutions include Cadence TripleCheck^™ technology, which provides users with a specification-compliant verification plan linked to comprehensive coverage models and a test suite to ensure compliance with the interface specification. The new VIP also support the expanded Cadence System-Level Verification IP (System VIP), which provides SoC-level test libraries, performance analysis, and data and cache coherency checkers. Using the expanded System VIP portfolio, customers can experience up to 10X efficiency improvements compared to a manual process for SoC verification.

“The Cadence memory VIP is a critical part of our verification process and instrumental in the successful deployment of our memory PHY IP,” said Ricky Lau, co-founder and CTO of The Six Semiconductor Inc. “Cadence continues to deliver new VIP offerings and advanced SoC verification technologies that support the latest standards. The Cadence VIP offerings have significantly reduced our development time and increased the confidence of our customers.”

“As requirements evolve and demand increases for higher bandwidth, lower power and more effective cache coherency management, new protocols arrive to address these issues,” said Paul Cunningham, senior vice president and general manager of the System & Verification Group at Cadence. “With these 13 new VIP, Cadence is offering customers solutions to ensure the designs comply with the standard specifications as well as application-specific timing, power and performance metrics, providing the fastest path to IP and SoC verification closure.”

The new VIP solutions are part of the broader Cadence verification full flow, which includes Palladium^® Z2 emulation, Protium^™ X2 prototyping, Xcelium^™ simulation, the Jasper^™ Formal Verification Platform, the Helium^™ Virtual and Hybrid Studio, and the Verisium^™ AI-Driven Verification Platform. The Cadence verification full flow delivers the highest verification throughput of bugs per dollar invested per day. The VIP solutions and verification full flow support the company’s Intelligent System Design^™ strategy, enabling SoC design excellence. For more information, please visit www.cadence.com/go/NewVIP2023.

About Cadence

Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For eight years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.

© 2023 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. Arm and AMBA are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. MIPI, A-PHY and SoundWire are registered trademarks owned by MIPI Alliance. UCIe Consortium, Universal Chiplet Interconnect Express, and UCIe are trademarks of the UCIe Consortium. All other trademarks are the property of their respective owners.

Category: Featured

View source version on businesswire.com: https://www.businesswire.com/news/home/20230216005110/en/

Cadence Newsroom

408-944-7039

newsroom@cadence.com

Source: Cadence Design Systems, Inc.

FAQ

What are the new VIP solutions launched by CDNS?

Cadence launched 13 new Verification IP solutions for enhanced SoC verification.

When were the new Verification IP solutions announced by Cadence?

The new Verification IP solutions were announced today.

How do the new Cadence VIP solutions improve verification?

They provide a consistent API and comprehensive coverage models, increasing efficiency by up to 10X.

What industry standards do the new CDNS VIP solutions support?

They support standards such as Arm AMBA 5 CHI-f, UCIe, GDDR7, and DDR5 DIMM.

What impact do the new VIP solutions have on SoC design?

The new VIP solutions enhance compliance and performance verification for SoC designs.