Cadence Collaborates with GUC on AI, HPC and Networking in Advanced Packaging Technologies

Rhea-AI Summary

Cadence Design Systems (NASDAQ: CDNS) has achieved a significant milestone by successfully validating the 112G-LR SerDes technology on Global Unichip Corp's (GUC) HBM3/GLink/CoWoS platform. This collaboration enhances Cadence's reputation in high-performance connectivity for advanced cloud data centers.

The 112G-LR SerDes integrates with GUC's innovative CoWoS platform and meets high-speed signal integrity requirements. It supports multiple data rates, including 112Gbps in PAM4 mode. The partnership is positioned to facilitate scalable solutions in AI, HPC, and networking.

Key industry leaders praised the collaboration, highlighting its potential to innovate packaging solutions. This development further solidifies Cadence's position in the semiconductor industry, reinforcing their Intelligent System Design strategy.

Positive

• Successful validation of the 112G-LR SerDes technology on GUC's platform enhances Cadence's market position.
• Partnership with GUC expands potential applications in AI, HPC, and networking.
• 112G-LR SerDes supports various data rates, optimizing performance for advanced packaging technologies.

Negative

• None.

Cadence 112G-LR SerDes silicon proven in GUC’s HBM3/GLink/CoWoS platform

SAN JOSE, Calif.--(BUSINESS WIRE)-- Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that the Cadence^® 112G-LR SerDes is silicon proven on the HBM3/GLink/CoWoS platform from Global Unichip Corp. (GUC). This milestone in the companies’ ongoing and successful collaboration solidifies Cadence’s leadership in high-performance connectivity IP for the high-bandwidth, high-reliability products that power the most advanced cloud data centers.

GUC’s big-die CoWoS platform represents real-world CPU, GPU, AI, and networking chips by integrating multiple instances of the Cadence 112G-LR SerDes with a 7.2Gbps HBM3 controller and PHY, as well as a GLink-2.5D die-to-die IP in the TSMC N7 process. Cadence collaborated with GUC on the interposer design to meet the strict high-speed signal integrity (SI) and power integrity (PI) requirements of 112G-LR SerDes signaling through silicon (CoWoS-S) and organic (CoWoS-R) interposers. The 112G-LR SerDes has been validated in the GUC CoWoS platform, demonstrating excellent performance and robustness in large-scale AI/HPC/networking chip conditions.

“Our AI/HPC/networking platform on TSMC’s CoWoS^® technology meets high-power and high-speed requirements at the system level and demonstrates our industry leadership in delivering complete advanced packaging solutions,” said Igor Elkanovich, CTO at GUC. “Cadence’s robust, production-quality 112G SerDes was instrumental in allowing us to unleash new potential for scalable, multi-die AI, HPC and networking solutions.”

“The successful demonstration of the Cadence 112G-LR SerDes in GUC’s platform using TSMC’s CoWoS technology is a great example of design ecosystem collaboration on 2.5D multi-die packaging solutions,” said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. “Cadence’s leading IP solutions together with TSMC’s advanced technologies enable system-level innovations for AI/ML, HPC and networking applications.”

“Our successful collaboration with GUC exemplifies how Cadence is delivering SoC design excellence through our Intelligent System Design strategy,” said Sanjive Agarwala, corporate vice president and general manager of the IP Group at Cadence. “The Cadence 112G-LR/ELR PAM4 SerDes IP portfolio has been widely adopted by customers to enable AI, HPC, networking and 5G SoC designs. This milestone expands our collaboration, enabling GUC to prove their groundbreaking CoWoS platform and solidifying Cadence’s leadership in high-performance connectivity IP offerings.”

The Cadence 112G-LR SerDes incorporates industry-leading analog-to-digital converter (ADC) and digital signal processor (DSP) technology that delivers exceptional long-reach performance with superior margin and optimized power and area. The IP provides multi-rate support including 112/56Gbps in PAM4 mode, as well as 56Gbps and lower data rates in NRZ mode. The IP supports both standard and advanced packaging technologies.

The 112G-LR SerDes IP is part of the broader Cadence IP portfolio and supports the company’s Intelligent System Design Strategy, enabling SoC design excellence. For more information, please visit www.cadence.com/go/112gpr.

About Cadence

Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design^™ strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For nine years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at www.cadence.com.

© 2023 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

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Source: Cadence Design Systems, Inc.

FAQ

What is the significance of Cadence's 112G-LR SerDes milestone on GUC's platform?

The milestone validates Cadence's technology in high-speed connectivity, enhancing its reputation in advanced cloud data center applications.

How does the 112G-LR SerDes technology support AI and HPC solutions?

The 112G-LR SerDes enables scalable, high-performance configurations necessary for AI and HPC applications.

What are the data rates supported by the Cadence 112G-LR SerDes?

The Cadence 112G-LR SerDes supports multiple data rates, including 112Gbps in PAM4 mode.

When was the Cadence 112G-LR SerDes validated in GUC's CoWoS platform?

The validation was announced recently, marking a significant collaboration milestone between Cadence and GUC.

What is the impact of Cadence's partnership with GUC on the semiconductor industry?

The partnership strengthens Cadence's position as a leader in high-performance connectivity solutions, promoting innovation in semiconductor packaging.