Cadence Brings Verification IP to the Chip Level with New System VIP Solution

Rhea-AI Summary

Cadence Design Systems (Nasdaq: CDNS) launched its new Cadence System-Level Verification IP (System VIP) to enhance system-on-chip (SoC) verification. The suite automates testbench assembly, traffic generation, and performance analysis, achieving up to 10X efficiency in chip-level verification. Key components include the System Testbench Generator, System Traffic Libraries, System Performance Analyzer, and System Verification Scoreboard. The solution extends Cadence’s leadership in IP-level verification to chip-level challenges, ensuring better throughput and quality in complex SoC designs.

Positive

• Launch of Cadence System VIP improves verification efficiency by up to 10X.
• Supports automation in chip-level verification challenges, enhancing throughput.
• Positive feedback from industry leaders like Renesas and Arm confirms effectiveness.

Negative

• None.

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced Cadence^® System-Level Verification IP (System VIP), a new suite of tools and libraries for automating system-on-chip (SoC) testbench assembly, bus and CPU traffic generation, cache-coherency validation and system performance bottleneck analysis. Using Cadence System VIP, customers creating complex hyperscale, automotive, mobile and consumer chips can improve chip-level verification efficiency by up to 10X.

For more information about Cadence System VIP, please visit http://www.cadence.com/go/SystemVIPpr.

The new Cadence System VIP solution takes Cadence’s market leadership in IP-level verification automation and brings it to the chip level. Tests created using the Cadence System VIP solution are portable across Cadence simulation, emulation and prototyping engines and can also be extended to post-silicon bring-up. Cadence System VIP consists of four new tools and libraries:

• System Testbench Generator: Allows users to automatically generate SoC testbenches with complex memory, cache, interface and bus configurations
• System Traffic Libraries: Provide users with a rich portfolio of pre-defined tests that can be plugged into a System VIP testbench, including coherency, performance, PCI Express^® (PCIe^®) and NVMe subsystems
• System Performance Analyzer: Offers comprehensive performance analysis reporting and visualization for memory subsystems, interconnects and peripherals
• System Verification Scoreboard: Provides comprehensive data and cache-coherency checks across coherent interconnects, memories and peripherals

“Renesas has used Cadence VIP for many years and values Cadence’s leadership in advanced SoC verification technologies,” said Tetsuya Asano, director, Design Methodology Department, Shared R&D EDA Division at Renesas. “By adding the new System VIP to our existing verification environment based on the Cadence Xcelium and Palladium platforms, and improving stimulus re-use and automation, we’ve further accelerated the SoC verification process with 10X more efficiency, enabling us to deliver innovative, high-quality products to our customers faster.”

“Through our collaboration with Cadence, we’ve reduced some of the complex SoC verification challenges, especially around I/O peripherals,” said Tran Nguyen, director of Design Services at Arm. “By using Cadence System Traffic Libraries and System Performance Analyzers, Arm was able to automate complex test generation processes, enabling a quicker PCIe integration verification and performance analysis.”

“Verification challenges increase exponentially as the number and complexity of integrated IP blocks on an SoC grow,” said Paul Cunningham, corporate vice president and general manager of the System & Verification Group at Cadence. “Our new Cadence System VIP solution dramatically improves verification throughput by automating some of today’s most critical labor-intensive chip-level verification challenges.”

The Cadence System VIP tool suite is part of the broader Cadence Verification Suite and supports the company’s Intelligent System Design^™ strategy. The Cadence Verification Suite is comprised of core engines and smart verification technologies that increase verification throughput and design quality, fulfilling verification requirements for a wide variety of applications and vertical segments.

About Cadence
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace, industrial and healthcare. For six years in a row, Fortune Magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at www.cadence.com.

© 2020 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. PCI Express and PCIe are registered trademarks or trademarks of PCI-SIG. All other trademarks are the property of their respective owners.