Cadence Achieves PCIe 5.0 Specification Compliance for PHY and Controller IP in TSMC Advanced Technologies

Rhea-AI Summary

Cadence Design Systems (CDNS) announced that its PCI Express 5.0 PHY and Controller IP has passed PCI-SIG certification tests at the first compliance event in April. The solutions achieved a speed of 32GT/s, aimed at SoC designs for hyperscale computing and networking. This certification enhances Cadence's position as a provider of power-efficient SoCs, aiding in faster market delivery. Key partnerships with TSMC and Intel further bolster their technological reputation. The PCIe 5.0 Design Kits are now available for licensing on TSMC N7, N6, and N5 processes.

Positive

• PCIe 5.0 PHY and Controller IP passed PCI-SIG certification, enhancing market credibility.
• Achieved full PCIe 5.0 speed of 32GT/s, indicating high performance.
• Focus on power-efficient SoCs aligns with current market demands.
• Strategic collaborations with TSMC and Intel for advanced technology support.

Negative

• None.

SAN JOSE, Calif.--(BUSINESS WIRE)-- Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that its PHY and Controller IP for the PCI Express^® (PCIe^®) 5.0 specification in the TSMC N7, N6 and N5 process technologies have passed certification tests from PCI-SIG^® at the industry’s first event for PCIe 5.0 specification compliance held in April. The Cadence^® solutions were tested to their full potential and complied with the full speed of 32GT/s for PCIe 5.0 technology. The compliance program provides designers with testing procedures to assess that the PCIe 5.0 interfaces on their system-on-chip (SoC) designs will operate as expected.

The Cadence IP for PCIe 5.0 technology consists of a PHY, companion controller and Verification IP (VIP) targeted at SoC designs for very high-bandwidth hyperscale computing, networking and storage applications. With Cadence’s PHY and Controller Subsystem for PCIe 5.0 architecture, customers can design extremely power-efficient SoCs while accelerating time to market.

“We are pleased Cadence has certified its comprehensive IP family for compliance with the PCIe 5.0 protocol on TSMC’s advanced processes,” said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. “Our continued close collaboration with Cadence is helping our mutual customers meet the stringent power and performance requirements and accelerate silicon innovation with leading-edge design solutions benefiting from TSMC’s advanced technologies.”

“With the lowest power consumption in the market as validated by our customers, Cadence’s certified PHY and Controller IP for PCIe 5.0 enables them to develop extremely power-efficient SoCs,” said Sanjive Agarwala, corporate vice president and general manager of the IP Group at Cadence. “With our multi-lane subsystem-on-a-chip solution, our customers can see IP compliance being achieved in form factors that match their target applications.”

“Consistent with previous testing, Cadence’s PHY and controller test chips for the PCIe 5.0 specification showed robust performance in compliance tests on our Xgig exerciser and analyzer platform,” said Tom Fawcett, senior vice president and general manager, Lab & Production Business Unit, VIAVI Solutions. “Cadence is at the leading edge of high-bandwidth hyperscale SoC IP, and their successful track record in PCI-SIG compliance events should project continued confidence in their solutions and the technology as a whole.”

“Intel is dedicated to industry-wide innovation and rigorous compatibility testing through the open PCI Express standard,” said Jim Pappas, director of Technology Initiatives, Intel Corporation. “Cadence’s latest PHY and Controller IP demonstrate their commitment to PCIe 5.0 performance and interoperability with our 12th Gen Intel Core and 4th Gen Intel Xeon Scalable platforms.”

“As a long-standing PCI-SIG member, Cadence plays a role in the advancement of PCIe technology,” said Al Yanes, President and Chairperson of PCI-SIG. “By participating in the compliance program, Cadence is helping to further the continued adoption of the PCIe architecture.”

The Cadence IP for PCIe 5.0 architecture supports the company’s Intelligent System Design^™ strategy, which enables advanced-node SoC design excellence. The PCIe 5.0 Design Kits for TSMC’s N7, N6 and N5 process technologies are available for licensing and delivery now. Cadence’s comprehensive portfolio of design IP solutions in the TSMC advanced processes also includes 112G, 56G, die-to-die (D2D) and advanced memory IP solutions.

For more information on Cadence IP for PCIe 5.0 technology, please visit www.cadence.com/go/pcie5pr. More information on Cadence IP for PCIe offerings can be found at www.cadence.com/go/pcieresources.

About Cadence

Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For eight years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.

About PCI-SIG

PCI-SIG is the consortium that owns and manages PCI specifications as open industry specifications. The organization defines I/O (input/output) specifications consistent with the needs of its members. Currently, PCI-SIG is comprised of nearly 900 industry-leading member companies. To join PCI-SIG, and for a list of the Board of Directors, visit www.pcisig.com.

© 2022 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. PCI-SIG, PCIe and the PCI Express are US registered trademarks and/or service marks of PCI-SIG. All other trademarks are the property of their respective owners.

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Source: Cadence Design Systems, Inc.

FAQ

What did Cadence Design Systems announce on PCIe 5.0?

Cadence announced that its PCI Express 5.0 PHY and Controller IP passed PCI-SIG certification, achieving a speed of 32GT/s.

How does the PCIe 5.0 IP support SoC designs?

The PCIe 5.0 solutions facilitate power-efficient SoC designs aimed at hyperscale computing and networking applications.

Which process technologies are compatible with Cadence's PCIe 5.0 Design Kits?

The Design Kits are compatible with TSMC's N7, N6, and N5 process technologies.

Why is the PCI-SIG certification important for Cadence?

PCI-SIG certification enhances Cadence's credibility and assures customers of compliance with industry standards.

What is the significance of the collaboration with TSMC and Intel?

The collaboration aids in meeting stringent power and performance requirements for advanced silicon products.