Cadence Accelerates Cloud Hyperscale Infrastructure with Third-Generation 112G-LR SerDes IP on TSMC’s N5 Process

Rhea-AI Summary

Cadence Design Systems (Nasdaq: CDNS) launched its third-generation 112G long-reach SerDes IP on TSMC’s N5 process, targeting hyperscale ASICs and AI/ML accelerators. The new architecture achieves 25% power savings and a 40% area reduction compared to the previous generation. It supports high-bandwidth, reliable products for cloud data centers. With improvements in DSP and supply noise immunity, Cadence enhances performance for chip connectivity. The company leverages collaborations with major customers to drive innovation, reinforcing its leadership in high-performance connectivity solutions.

Positive

• 25% power savings and 40% area reduction in new 112G-LR SerDes IP.
• Improved DSP with robust performance and enhanced supply noise immunity.
• Strong collaborations with leading hyperscale and data center customers.

Negative

• None.

Cadence Design Systems, Inc. (Nasdaq: CDNS) today unveiled its third-generation 112G long-reach (112G-LR) SerDes IP on TSMC’s N5 process for hyperscale ASICs, artificial intelligence/machine learning (AI/ML) accelerators, and switch fabric systems on chip (SoCs). The Cadence^® 112G-LR PAM4 SerDes IP on TSMC’s N5 process delivers the power, performance and area (PPA) efficiency required to build the high-bandwidth and high-reliability products for next-generation cloud data centers. The innovative architecture offers 25% power savings, 40% area reduction and better design margins over the second-generation architecture, satisfying the increasing needs for higher performance and power efficiency in today’s data centers.

Cadence has built a large customer base by enabling different variances of PAM4 SerDes supporting XSR, VSR, MR and LR interconnect standards. Through various 112G-LR SerDes design wins and deep collaborations with leading hyperscale and data center customers, Cadence has incorporated specific enhancements in the third-generation product and currently has N5 test chips in-house that are undergoing characterization. Cadence has been working closely with early adopter customers on deploying the new 112G-LR SerDes IP in their 5nm SoC development and is ready to engage broadly with customers to enable next-generation designs. For more information on the 112G-LR SerDes, please visit www.cadence.com/go/112gserdesn5.

With the improved architecture, Cadence now offers an enhanced DSP with multiple floating decision feedback equalization (DFE) taps to enable more robust performance. The 1-112G gapless data rate support provides excellent I/O flexibility for chip-to-chip connectivity for AI/ML accelerator SoCs. In addition, a 10X improvement in supply noise immunity greatly eases the SoC power delivery network (PDN) design.

“Our next-generation 112G-LR SerDes on TSMC N5 solution offers 25% power savings, 40% area reduction and better design margins over the previous generation,” said Sanjive Agarwala, corporate vice president and general manager of the IP Group at Cadence. “Our close collaborations with leading hyperscale and data center customers have given us the insights into the stringent industry requirements, resulting in a new design with enhanced architecture that offers improvements on all the key parameters for 112G SerDes and network switches. Our 112G-LR SerDes solution on TSMC’s N5 process further solidifies our leadership position with high-performance connectivity IP offerings for hyperscale data centers, and customers can also enjoy the benefits associated with the TSMC N5 process technology.”

The 112G-LR SerDes IP on TSMC’s N5 process is part of the broader Cadence IP portfolio and supports the Cadence Intelligent System Design^™ strategy, which enables advanced-node SoC design excellence.

About Cadence

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications, including consumer, hyperscale computing, 5G communications, automotive, mobile, aerospace, industrial and healthcare. For seven years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.

© 2021 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

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FAQ

What are the key features of Cadence's new 112G-LR SerDes IP?

Cadence's 112G-LR SerDes IP offers 25% power savings, 40% area reduction, and improved DSP for robust performance.

How does the 112G-LR SerDes IP support AI/ML applications?

The 112G-LR SerDes IP is designed to enhance connectivity and performance for AI/ML accelerator SoCs.

What technology is used for the new 112G-LR SerDes IP?

The new SerDes IP is built on TSMC’s 5nm(N5) process technology.

What advantages does the 112G-LR SerDes IP offer for data centers?

It provides greater power efficiency and area reduction, essential for building high-bandwidth products for cloud data centers.

When was the 112G-LR SerDes IP announced?

Cadence announced the 112G-LR SerDes IP on May 24, 2021.