ASE Demonstrates CPO that Improves Energy Efficiency for AI applications
ASE (NYSE: ASX) has unveiled a groundbreaking co-packaged optics (CPO) device that significantly improves energy efficiency for AI applications. The device mounts multiple optical engines directly onto a substrate, achieving power consumption of less than 5pJ/bit and substantial bandwidth improvements.
The innovation addresses critical data center challenges by enhancing latency, data throughput, and scalability. Compared to current faceplate-pluggable solutions at 30pJ/bit and on-board solutions at 20pJ/bit, ASE's CPO scales to less than 5pJ/bit. The technology solves the assembly challenge of multiple optical engines with an ASIC in an integrated package with a large body configuration of >75mm X 75mm.
This development is particularly timely as IDC projects AI silicon in data centers to grow at 24.9% CAGR from 2024 to 2028, while McKinsey forecasts data center capacity demand to rise at 27% CAGR from 2023 to 2030, reaching 298 GigaWatts annually.
ASE (NYSE: ASX) ha presentato un dispositivo innovativo di ottica co-imballata (CPO) che migliora significativamente l'efficienza energetica per le applicazioni di intelligenza artificiale. Il dispositivo monta più motori ottici direttamente su un substrato, raggiungendo un consumo energetico di meno di 5pJ/bit e notevoli miglioramenti della larghezza di banda.
L'innovazione affronta sfide critiche nei data center migliorando la latenza, il throughput dei dati e la scalabilità. Rispetto alle attuali soluzioni pluggabili a facciata a 30pJ/bit e alle soluzioni on-board a 20pJ/bit, il CPO di ASE si scalda a meno di 5pJ/bit. La tecnologia risolve la sfida dell'assemblaggio di più motori ottici con un ASIC in un pacchetto integrato con una configurazione di grande corpo di >75mm X 75mm.
Questo sviluppo è particolarmente tempestivo poiché IDC prevede che il silicio per intelligenza artificiale nei data center crescerà a 24,9% CAGR dal 2024 al 2028, mentre McKinsey prevede che la domanda di capacità nei data center aumenterà a 27% CAGR dal 2023 al 2030, raggiungendo annualmente 298 GigaWatt.
ASE (NYSE: ASX) ha revelado un dispositivo innovador de óptica coempaquetada (CPO) que mejora significativamente la eficiencia energética para aplicaciones de inteligencia artificial. El dispositivo monta múltiples motores ópticos directamente sobre un sustrato, logrando un consumo de energía de menos de 5pJ/bit y mejoras sustanciales en el ancho de banda.
La innovación aborda desafíos críticos en los centros de datos al mejorar la latencia, el rendimiento de datos y la escalabilidad. En comparación con las soluciones actuales enchufables en la placa frontal a 30pJ/bit y las soluciones a bordo a 20pJ/bit, el CPO de ASE se escala a menos de 5pJ/bit. La tecnología resuelve el desafío de ensamblar múltiples motores ópticos con un ASIC en un paquete integrado con una configuración de cuerpo grande de >75mm X 75mm.
Este desarrollo es particularmente oportuno, ya que IDC proyecta que el silicio de IA en los centros de datos crecerá a 24.9% CAGR de 2024 a 2028, mientras que McKinsey pronostica que la demanda de capacidad en los centros de datos aumentará a 27% CAGR de 2023 a 2030, alcanzando 298 GigaWatts anualmente.
ASE (NYSE: ASX)는 인공지능 애플리케이션을 위한 에너지 효율성을 크게 향상시키는 혁신적인 공동 패키징 광학 장치(CPO)를 공개했습니다. 이 장치는 여러 광학 엔진을 기판에 직접 장착하여 5pJ/bit 미만의 전력 소비와 상당한 대역폭 개선을 달성합니다.
이 혁신은 지연 시간, 데이터 처리량 및 확장성을 향상시켜 데이터 센터의 주요 문제를 해결합니다. 현재의 프론트 플레이트 플러그형 솔루션이 30pJ/bit, 온보드 솔루션이 20pJ/bit인 것과 비교할 때, ASE의 CPO는 5pJ/bit 미만으로 확장됩니다. 이 기술은 >75mm X 75mm의 대형 패키지 구성에서 ASIC과 함께 여러 광학 엔진의 조립 문제를 해결합니다.
이 개발은 IDC가 데이터 센터의 AI 실리콘이 2024년부터 2028년까지 24.9% CAGR로 성장할 것이라고 예상하고, McKinsey가 데이터 센터 용량 수요가 2023년부터 2030년까지 27% CAGR로 증가할 것이라고 예측하는 시점에 특히 시기적절합니다. 연간 298 기가와트에 도달합니다.
ASE (NYSE: ASX) a dévoilé un dispositif révolutionnaire d'optique co-emballé (CPO) qui améliore considérablement l'efficacité énergétique pour les applications d'intelligence artificielle. Le dispositif monte plusieurs moteurs optiques directement sur un substrat, atteignant une consommation d'énergie inférieure à 5pJ/bit et des améliorations substantielles de la bande passante.
L'innovation répond à des défis critiques des centres de données en améliorant la latence, le débit de données et l'évolutivité. Comparé aux solutions à plaque frontale actuelles à 30pJ/bit et aux solutions embarquées à 20pJ/bit, le CPO d'ASE se développe à moins de 5pJ/bit. La technologie résout le défi de l'assemblage de plusieurs moteurs optiques avec un ASIC dans un package intégré avec une configuration de grande taille de >75mm X 75mm.
Ce développement est particulièrement opportun car IDC prévoit que le silicium IA dans les centres de données croîtra à 24,9% CAGR de 2024 à 2028, tandis que McKinsey prévoit que la demande de capacité des centres de données augmentera à 27% CAGR de 2023 à 2030, atteignant 298 GigaWatts par an.
ASE (NYSE: ASX) hat ein bahnbrechendes Co-Package-Optikgerät (CPO) vorgestellt, das die Energieeffizienz für KI-Anwendungen erheblich verbessert. Das Gerät montiert mehrere optische Motoren direkt auf einem Substrat und erreicht einen Stromverbrauch von weniger als 5pJ/bit sowie erhebliche Verbesserungen der Bandbreite.
Die Innovation adressiert kritische Herausforderungen in Rechenzentren, indem sie Latenz, Daten-Durchsatz und Skalierbarkeit verbessert. Im Vergleich zu aktuellen Frontplattenstecklösungen mit 30pJ/bit und Onboard-Lösungen mit 20pJ/bit skaliert ASEs CPO auf weniger als 5pJ/bit. Die Technologie löst die Montageherausforderung mehrerer optischer Motoren mit einem ASIC in einem integrierten Paket mit einer großen Gehäusekonfiguration von >75mm X 75mm.
Diese Entwicklung ist besonders zeitgemäß, da IDC prognostiziert, dass KI-Silizium in Rechenzentren von 2024 bis 2028 mit 24,9% CAGR wachsen wird, während McKinsey eine Steigerung der Nachfrage nach Rechenzentrums-Kapazitäten von 27% CAGR von 2023 bis 2030 vorhersagt, was jährlich 298 Gigawatt erreicht.
- Achieves significant power efficiency improvement to <5pJ/bit from current 20-30pJ/bit solutions
- Enables substantial bandwidth increases and improved data throughput
- Reduces costs per bit through improved design efficiency
- Provides integration solution for CPUs, GPUs, and XPUs with optics in a single package
- Addresses growing market demand with AI silicon growth projected at 24.9% CAGR
- None.
Insights
ASE's co-packaged optics (CPO) demonstration represents a significant technological leap in advanced packaging for AI applications. By mounting optical engines directly onto substrates, they've achieved power consumption of
What makes this development particularly notable is how it addresses the semiconductor industry's power wall challenge. As AI workloads intensify, the electrical interconnect power consumption increasingly dominates total system power. By shortening electrical paths and reducing insertion loss, ASE's approach eliminates the need for power-hungry retimer chips while significantly improving signal integrity.
The technical achievement of integrating multiple optical engines with an ASIC in packages exceeding 75mm × 75mm shouldn't be underestimated. This overcomes substantial manufacturing challenges related to substrate warpage and coplanarity control for fiber array coupling - critical barriers that have previous CPO implementations.
This innovation positions ASE strongly in the advanced packaging hierarchy, offering a compelling bridge technology between current solutions and future fully integrated 3D CPO. As part of their VIPack™ platform and supported by their Integrated Design Ecosystem, this demonstrates ASE's systematic approach to advanced packaging rather than an isolated development.
ASE's CPO technology addresses three critical pain points currently plaguing data center operators handling AI workloads: power constraints, bandwidth limitations, and system density.
Power efficiency has become the dominant bottleneck in AI infrastructure scaling. McKinsey's projection of
The timing couldn't be more strategic given IDC's forecast of
What's particularly valuable is the dual-market applicability: for networking applications, this technology provides an upgrade path for 1.6Tb/s and 3.2Tb/s optical interconnects while enabling ultra-low latency options. For compute environments, it creates a pathway to integrate CPUs, GPUs, and other accelerators with optics in unified packages.
This development matters because data center operators increasingly face hard power limits that constrain their ability to deploy AI infrastructure at scale. Technologies that dramatically improve power efficiency while simultaneously enhancing bandwidth, latency, and scalability address the most pressing constraints in modern data center design.
Advanced Semiconductor Engineering, Inc. (ASE), a member of ASE Technology Holding Co., Ltd. (NYSE: ASX, TAIEX: 3711), today announced that it has demonstrated a co-packaged optics (CPO) device that mounts multiple optical engines (OE) directly onto a substrate, enabling <5pJ/bit power consumption and significant bandwidth increases. With today’s processing power requirements being extremely amplified by AI pervasion, there is unprecedented demand for bandwidth that must be addressed. ASE’s new configuration enables crucial on-package energy efficiency and bandwidth expansion while addressing further data center challenges by delivering improvement related to latency, data throughput, and scalability.
According to IDC (Jan 2025), the proliferation of AI silicon in the data center will experience
As bandwidth demands grow exponentially, the current faceplate-pluggable (FPP) solutions show roadmap limitations in density, power, and cost. The increasing switch speeds also lead to an increase in SerDes interconnect power as a percentage of the total switch power. This is driving the need to move the optics from the FPP into the enclosure closer to the switch ASIC. On-board optics have been adopted as a first step, and ASE’s CPO provides an attractive option that has lower insertion loss, resulting in reduced power consumption and cost/bit. From a pJ/bit comparison, FPP solutions are currently 30pJ/bit, while on-board solutions are 20pJ/bit, but now scaling <5pJ/bit through CPO.
ASE’s CPO solves the assembly challenge of multiple optical engines with an ASIC in an integrated package with a large body configuration of >75mm X 75mm. The benefits for both the networking and data center markets are significant. For networking, it provides a potential option to improve or replace pluggable optics at 1.6Tb/s or 3.2 Tb/s, as well as an integration solution that enables ultra-low latency option for CPO. For compute, the platform can be used to integrate the CPUs, GPUs, XPUs with the optics into a single co-packaged solution through high-speed optical data links.
“Global demand for data center capacity could rise at
“Our industry has moved beyond classical compute into the high-performance compute era where data center demands are being highly influenced by advanced AI models and applications, power consumption, and ongoing cloud and edge compute dynamics,” added Yin Chang, Executive Vice President, ASE. “These present massive challenges, particularly related to power and cooling limitations, and require our industry to deliver breakthrough innovations that facilitate application and scale. At ASE, we are committed to taking silicon photonics to a new level and augmenting our customer value through delivering CPO technology that demonstrates superior energy efficiency at this critical juncture in AI permeation.”
ASE’s CPO is part of VIPack™, which is a scalable platform expanding in alignment with industry roadmaps, and supported by its Integrated Design Ecosystem™ (IDE), a collaborative design toolset optimized to systematically boost advanced package architecture.
ASE will be represented at the Optical Fiber Conference 2025 in San Francisco this week by Dr. CP Hung, VP of R&D, who will deliver a presentation titled, ‘Latest Advanced Packaging Solutions for AI’, scheduled for Thursday April 3rd 15:15 - 15:45 in the Packaging and Coupling Techniques session.
Supporting resources
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About ASE, Inc.
ASE, Inc. is the leading global provider of semiconductor manufacturing services in assembly and test. Alongside a broad portfolio of established assembly and test technologies, ASE is also delivering innovative VIPack™, advanced packaging, and system-in-package solutions to meet growth momentum across a broad range of end markets, including AI, Automotive, 5G, High-Performance Computing, and more. To learn about our advances in SiP, Fanout, MEMS & Sensor, Flip Chip, and 2.5D, 3D & TSV technologies, all ultimately geared towards applications to improve lifestyle and efficiency, please visit: aseglobal.com or follow us on LinkedIn & X: @aseglobal.
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Source: Advanced Semiconductor Engineering, Inc.
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