Arteris Network-on-Chip Tiling Innovation Accelerates Semiconductor Designs for AI Applications
Arteris, Inc. (Nasdaq: AIP) has announced an innovative evolution of its network-on-chip (NoC) IP products with tiling capabilities and extended mesh topology support for faster development of AI and ML compute in SoC designs. This new functionality enables design teams to scale compute performance by more than 10 times while meeting project schedules and PPA goals.
Key benefits include:
- Scalable Performance: Easily scale systems-on-chip with AI by more than 10 times without changing the basic design
- Power Reduction: Network-on-chip tiles can be turned off dynamically, cutting power by 20% on average
- Design Reuse: Pre-tested network-on-chip tiles can be reused, cutting SoC integration time by up to 50%
The combination of tiling and mesh topologies in Arteris' FlexNoC and Ncore products can reduce XPU sub-system design time and overall SoC connectivity execution time by up to 50% compared to manually integrated, non-tiled designs.
Arteris, Inc. (Nasdaq: AIP) ha annunciato un'evoluzione innovativa dei suoi prodotti IP network-on-chip (NoC) con capacità di tiling e supporto per una topologia mesh estesa per uno sviluppo più rapido del calcolo AI e ML nei progetti SoC. Questa nuova funzionalità consente ai team di design di scalare le prestazioni computazionali di oltre 10 volte rispettando al contempo i tempi di progetto e gli obiettivi di PPA.
I principali vantaggi includono:
- Prestazioni Scalabili: Scala facilmente i sistemi-on-chip con AI di oltre 10 volte senza modificare il design di base
- Riduzione del Consumo Energetico: I tile del network-on-chip possono essere spenti dinamicamente, riducendo in media il consumo energetico del 20%
- Riutilizzo del Design: I tile del network-on-chip già testati possono essere riutilizzati, riducendo il tempo di integrazione del SoC fino al 50%
La combinazione di tiling e topologie mesh nei prodotti FlexNoC e Ncore di Arteris può ridurre il tempo di design del subsistema XPU e il tempo di esecuzione della connettività complessiva del SoC fino al 50% rispetto a design non tilizzati e integrati manualmente.
Arteris, Inc. (Nasdaq: AIP) ha anunciado una evolución innovadora de sus productos IP de red en chip (NoC) con capacidades de mosaico y soporte extendido para topologías de malla para un desarrollo más rápido de computación IA y ML en diseños de SoC. Esta nueva funcionalidad permite a los equipos de diseño escalar el rendimiento computacional en más de 10 veces mientras cumplen con los plazos del proyecto y los objetivos de PPA.
Los principales beneficios incluyen:
- Rendimiento Escalable: Aumenta fácilmente los sistemas en chip con IA en más de 10 veces sin cambiar el diseño básico
- Reducción de Energía: Los mosaicos de red en chip se pueden apagar dinámicamente, reduciendo el consumo de energía en un 20% en promedio
- Reutilización del Diseño: Los mosaicos de red en chip previamente probados pueden reutilizarse, reduciendo el tiempo de integración del SoC en hasta un 50%
La combinación de mosaicos y topologías de malla en los productos FlexNoC y Ncore de Arteris puede reducir el tiempo de diseño del subsistema XPU y el tiempo total de ejecución de conectividad SoC en hasta un 50% en comparación con diseños no mosaicos integrados manualmente.
Arteris, Inc. (Nasdaq: AIP)는 타일링 기능과 확장된 메시 토폴로지 지원을 갖춘 네트워크온칩(NoC) IP 제품의 혁신적인 진화를 발표했습니다. 이는 SoC 설계에서 AI 및 ML 컴퓨팅의 개발을 더욱 가속화합니다. 이 새로운 기능은 설계 팀이 컴퓨팅 성능을 10배 이상 확장할 수 있도록 하여 프로젝트 일정과 PPA 목표를 충족할 수 있게 해줍니다.
주요 이점은 다음과 같습니다:
- 확장 가능한 성능: 기본 설계를 변경하지 않고 AI가 포함된 시스템온칩의 성능을 10배 이상 쉽게 확장할 수 있습니다.
- 전력 감소: 네트워크온칩 타일을 동적으로 꺼서 평균적으로 전력을 20% 감소시킬 수 있습니다.
- 설계 재사용: 미리 테스트한 네트워크온칩 타일을 재사용해 SoC 통합 시간을 최대 50% 단축할 수 있습니다.
Arteris의 FlexNoC 및 Ncore 제품에서의 타일링과 메시 토폴로지의 조합은 수동으로 통합된 비타일 디자인과 비교할 때 XPU 하위 시스템 설계 시간과 전체 SoC 연결 실행 시간을 최대 50%까지 줄일 수 있습니다.
Arteris, Inc. (Nasdaq: AIP) a annoncé une évolution innovante de ses produits IP réseau-sur-puce (NoC) avec des capacités de carrelage et un support élargi de topologie en maillage pour un développement plus rapide des calculs IA et ML dans les conceptions SoC. Cette nouvelle fonctionnalité permet aux équipes de conception de scaler les performances de calcul de plus de 10 fois tout en respectant les délais de projet et les objectifs de PPA.
Les principaux avantages incluent :
- Performance évolutive : Augmentez facilement les systèmes sur puce avec AI de plus de 10 fois sans changer la conception de base
- Réduction de la consommation d'énergie : Les carreaux de réseau sur puce peuvent être désactivés de manière dynamique, réduisant la consommation d'énergie en moyenne de 20%
- Réutilisation de design : Les carreaux de réseau sur puce prétestés peuvent être réutilisés, réduisant le temps d'intégration du SoC de jusqu'à 50%
La combinaison de carrelage et de topologies de maillage dans les produits FlexNoC et Ncore d'Arteris peut réduire le temps de conception du sous-système XPU et le temps d'exécution de connectivité globale du SoC jusqu'à 50 % par rapport aux conceptions non carrelées intégrées manuellement.
Arteris, Inc. (Nasdaq: AIP) hat eine innovative Weiterentwicklung seiner Network-on-Chip (NoC) IP-Produkte mit Fliesenfunktionen und erweiterter Mesh-Topologie-Unterstützung für eine schnellere Entwicklung von KI- und ML-Computing in SoC-Designs angekündigt. Diese neue Funktionalität ermöglicht es den Entwicklungsteams, die Rechenleistung um mehr als das 10-fache zu skalieren und dabei die Projektzeitpläne und PPA-Ziele einzuhalten.
Wesentliche Vorteile sind:
- Skalierbare Leistung: Systeme-on-Chip mit KI können um mehr als das 10-fache skaliert werden, ohne das grundlegende Design zu ändern
- Energieeinsparung: Network-on-Chip-Fliesen können dynamisch deaktiviert werden, was den Energieverbrauch im Durchschnitt um 20% senkt
- Designwiederverwendung: Vorgeprüfte Network-on-Chip-Fliesen können wiederverwendet werden, wodurch die SoC-Integrationszeit um bis zu 50% verkürzt wird
Die Kombination von Fliesen und Mesh-Topologien in den Produkten FlexNoC und Ncore von Arteris kann die Designzeit des XPU-Subsystems und die gesamte SoC-Konnektivitätsausführungszeit im Vergleich zu manuell integrierten, nicht gefliesten Designs um bis zu 50% reduzieren.
- Enables scaling of compute performance by more than 10 times for AI-enabled SoCs
- Reduces power consumption by 20% on average through dynamic tile power-off
- Cuts SoC integration time by up to 50% through reuse of pre-tested network-on-chip tiles
- Reduces XPU sub-system design time and SoC connectivity execution time by up to 50%
- Supports fast-growing AI workloads including Vision, ML, DL, NLP, LLMs, and Generative AI
- None.
Insights
Arteris' new network-on-chip (NoC) tiling innovation represents a significant advancement in SoC design for AI applications. The ability to scale compute performance by over 10 times while maintaining project schedules and PPA goals is a game-changer for the industry. This technology addresses critical challenges in AI chip design:
- Scalability: Enables easy scaling of AI systems without major design overhauls
- Power efficiency:
20% average power reduction through dynamic tile shutdown - Time-to-market: Up to
50% reduction in SoC integration time
The modular approach of soft tiles allows for faster integration and optimization, which is important in the rapidly evolving AI chip market. This innovation positions Arteris favorably against competitors and could lead to increased adoption of their IP in next-generation AI SoCs. For investors, this could translate to potential revenue growth and market share expansion in the burgeoning AI chip design space.
Arteris' NoC tiling innovation addresses key bottlenecks in AI chip design, particularly for edge AI applications. The ability to scale performance by 10x is important for handling increasingly complex AI workloads, including vision processing, NLP and generative AI. This technology enables:
- Efficient handling of large AI data volumes
- Support for sophisticated AI algorithms
- Scalability for diverse AI models (CNNs to multimodal GenAI)
The endorsement from SiMa.ai, an edge AI platform developer, underscores the practical value of this technology. By enabling more powerful and efficient edge AI devices, Arteris is positioning itself at the forefront of a rapidly growing market segment. This innovation could accelerate the deployment of advanced AI capabilities in various edge devices, potentially opening new revenue streams for Arteris in emerging AI applications.
Highlights:
- Scalable Performance: Expanded network-on-chip tiling supported by mesh topology capabilities in FlexNoC and Ncore interconnect IP products allow systems-on-chip with AI to easily scale by more than 10 times without changing the basic design, meeting AI's huge demand for faster and more powerful computing.
- Power Reduction: Network-on-chip tiles can be turned off dynamically, cutting power by
20% on average, essential for more energy-efficient and sustainable AI applications with lower operating costs.
- Design Reuse: Pre-tested network-on-chip tiles can be reused, cutting the SoC integration time by up to
50% and shortening the time to market for AI innovations.
CAMPBELL, Calif., Oct. 15, 2024 (GLOBE NEWSWIRE) -- Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP which accelerates system-on-chip (SoC) creation, today announced an innovative evolution of its network-on-chip (NoC) IP products with tiling capabilities and extended mesh topology support for faster development of Artificial Intelligence (AI) and Machine Learning (ML) compute in system-on-chip (SoC) designs. The new functionality enables design teams to scale compute performance by more than 10 times while meeting project schedules plus power, performance and area (PPA) goals.
Network-on-chip tiling is an emerging trend in SoC design. The evolutionary approach uses proven, robust network-on-chip IP to facilitate scaling, condense design time, speed testing and reduce design risk. It allows SoC architects to create modular, scalable designs by replicating soft tiles across the chip. Each soft tile represents a self-contained functional unit, enabling faster integration, verification and optimization.
Tiling coupled with mesh topologies within Arteris’ flagship NoC IP products, FlexNoC and Ncore, are transformative for the ever-growing inclusion of AI compute into most SoCs. AI-enabled systems are growing in size and complexity yet can be quickly scaled with the addition of soft tiles without disrupting the entire SoC design. Together, the combination of tiling and mesh topologies provides a way to further reduce the auxiliary processing unit (XPU) sub-system design time and overall SoC connectivity execution time by up to
The first iteration of NoC tiling organizes Network Interface Units (NIUs) into modular, repeatable blocks, improving scalability, efficiency and reliability in SoC designs. These SoC designs result in increasingly larger and more advanced AI compute which supports fast-growing, sophisticated AI workloads for Vision, Machine Learning (ML) models, Deep Learning (DL), Natural Language Processing (NLP) including Large Language Models (LLMs), and Generative AI (GAI), both for training and inference, including at the edge.
“Thanks to Arteris’ highly scalable and flexible mesh-based NoC IP, our SoC team has implemented support for larger AI data volumes and complex algorithms more efficiently. The close collaboration with Arteris has enabled us to create an Arm-based, multi-modal, software-centric edge AI platform that supports models ranging from CNNs to multimodal GenAI and everything in between with scalable performance per watt,” said Srivi Dhruvanarayan, VP of hardware engineering at SiMa.ai. “We look forward to deploying the expanded Arteris NoC tiling and mesh functionality, which should further enhance our ability to create highly scalable AI silicon platforms for the edge.”
“Arteris is continuously innovating, and this revolutionary NoC soft tiling functionality supported by large mesh topologies is an advancement in SoC design technology,” said K. Charles Janac, president and CEO of Arteris. “Our customers, who are already building leading-edge AI-powered SoCs, are further empowered to accelerate the development of much larger and more complex AI systems with greater efficiency, all while staying within their project timeline and PPA targets.”
The FlexNoC and Ncore NoC IP products, which offer expanded AI support via tiling and extended mesh topology capabilities, are now available to early-access customers and partners. To learn more, visit arteris.ai.
About Arteris
Arteris is a leading provider of system IP for the acceleration of system-on-chip (SoC) development across today's electronic systems. Arteris network-on-chip (NoC) interconnect IP and SoC integration automation technology enable higher product performance with lower power consumption and faster time to market, delivering better SoC economics so its customers can focus on dreaming up what comes next. Learn more at arteris.com.
© 2004-2024 Arteris, Inc. All rights reserved worldwide. Arteris, Arteris IP, the Arteris IP logo, and the other Arteris marks found at https://www.arteris.com/trademarks are trademarks or registered trademarks of Arteris, Inc. or its subsidiaries. All other trademarks are the property of their respective owners.
Media Contact:
Gina Jacobs
Arteris
+1 408 560 3044
newsroom@arteris.com
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